Report generated on 07-May-2025 at 03:03:13 by pytest-html v3.2.0
880 tests ran in 570.51 seconds.
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880 passed, 0 skipped, 0 failed, 0 errors, 0 expected failures, 0 unexpected passes| Result | Test | TIDL Subgraphs | Complete TIDL Offload | Duration | Links |
|---|---|---|---|---|---|
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| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_429] | 1 | True | 9.93 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.274s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2597s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2606s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19488129 bytes MEM: Free's : 27 free's of 19488129 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_440] | 1 | True | 18.82 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4179s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4194s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 22754369 bytes MEM: Free's : 27 free's of 22754369 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_52] | 1 | True | 15.45 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4065s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4080s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 22081141 bytes MEM: Free's : 27 free's of 22081141 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_220] | 1 | True | 18.89 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.486s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5904s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5918s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681781 bytes MEM: Free's : 26 free's of 18681781 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_144] | 1 | True | 18.79 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3592s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3606s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700365 bytes MEM: Free's : 27 free's of 18700365 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_343] | 1 | True | 22.43 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11065s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11086s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682193 bytes MEM: Free's : 26 free's of 18682193 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_236] | 1 | True | 15.59 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.303s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6073s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6093s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18711737 bytes MEM: Free's : 27 free's of 18711737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_269] | 1 | True | 15.31 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3520s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3535s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682773 bytes MEM: Free's : 26 free's of 18682773 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_66] | 1 | True | 9.66 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.375s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3435s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3446s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681101 bytes MEM: Free's : 26 free's of 18681101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_201] | 1 | True | 20.38 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7860s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7880s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18705977 bytes MEM: Free's : 27 free's of 18705977 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_230] | 1 | True | 18.99 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.514s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9023s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9053s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18702321 bytes MEM: Free's : 27 free's of 18702321 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_48] | 1 | True | 11.31 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.267s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3756s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3770s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 119417773 bytes MEM: Free's : 26 free's of 119417773 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_295] | 1 | True | 9.55 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3257s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3269s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18808237 bytes MEM: Free's : 26 free's of 18808237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_297] | 1 | True | 9.82 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3642s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3653s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18820553 bytes MEM: Free's : 27 free's of 18820553 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_391] | 1 | True | 18.59 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3843s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3858s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700069 bytes MEM: Free's : 27 free's of 18700069 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_95] | 1 | True | 9.58 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3029s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3045s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699661 bytes MEM: Free's : 27 free's of 18699661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_41] | 1 | True | 19.22 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 0 | ------------------------------------------------------------------------------ Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.309s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3537s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3554s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22938669 bytes MEM: Free's : 26 free's of 22938669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_217] | 1 | True | 9.18 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.505s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8241s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8277s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681233 bytes MEM: Free's : 26 free's of 18681233 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_6] | 1 | True | 19.57 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3739s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3770s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19434413 bytes MEM: Free's : 26 free's of 19434413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_157] | 1 | True | 21.07 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3858s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3873s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18704653 bytes MEM: Free's : 27 free's of 18704653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_271] | 1 | True | 9.45 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3779s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3797s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682797 bytes MEM: Free's : 26 free's of 18682797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_391] | 1 | True | 15.32 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 0 | ------------------------------------------------------------------------------ Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3602s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3618s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18669029 bytes MEM: Free's : 26 free's of 18669029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_173] | 1 | True | 22.00 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3579s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3595s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18780045 bytes MEM: Free's : 27 free's of 18780045 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_426] | 1 | True | 15.36 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.358s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4697s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4717s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19490129 bytes MEM: Free's : 27 free's of 19490129 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_59] | 1 | True | 35.23 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2913s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2925s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 752702661 bytes MEM: Free's : 27 free's of 752702661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_238] | 1 | True | 23.27 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9065s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9094s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693189 bytes MEM: Free's : 26 free's of 18693189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_18] | 1 | True | 22.00 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3678s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3689s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18779309 bytes MEM: Free's : 26 free's of 18779309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_12] | 1 | True | 14.96 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 0 | ------------------------------------------------------------------------------ Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.535s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10798s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10826s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18794877 bytes MEM: Free's : 26 free's of 18794877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_149] | 1 | True | 16.44 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.589s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9907s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9939s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700653 bytes MEM: Free's : 27 free's of 18700653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_121] | 1 | True | 13.23 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.526s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10276s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10305s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18731901 bytes MEM: Free's : 27 free's of 18731901 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_93] | 1 | True | 13.99 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10238s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10264s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681429 bytes MEM: Free's : 26 free's of 18681429 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_262] | 1 | True | 21.55 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8252s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8271s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19467333 bytes MEM: Free's : 26 free's of 19467333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_419] | 1 | True | 11.52 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6629s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6654s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18897489 bytes MEM: Free's : 27 free's of 18897489 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_71] | 1 | True | 11.54 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.277s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4844s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4860s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700237 bytes MEM: Free's : 27 free's of 18700237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_135] | 1 | True | 14.92 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4252s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4262s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19206573 bytes MEM: Free's : 26 free's of 19206573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_402] | 1 | True | 18.27 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.449s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8318s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8350s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693437 bytes MEM: Free's : 26 free's of 18693437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_403] | 1 | True | 15.40 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.453s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8535s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8559s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18711761 bytes MEM: Free's : 27 free's of 18711761 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_310] | 1 | True | 16.35 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5768s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5790s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20575405 bytes MEM: Free's : 26 free's of 20575405 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_39] | 1 | True | 9.15 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.392s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7306s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7332s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23018413 bytes MEM: Free's : 26 free's of 23018413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_61] | 0 | - | 0.22 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------------------------------------------------- | Div | /Div | Layer /Div - op type Div, number of input dims(7) is not supported by TIDL, maximum dimension allowed is 6 | --------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_355] | 1 | True | 10.02 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.539s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7353s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7364s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18704473 bytes MEM: Free's : 27 free's of 18704473 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_439] | 1 | True | 12.14 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.516s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8279s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8301s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21853869 bytes MEM: Free's : 26 free's of 21853869 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_114] | 1 | True | 17.40 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9456s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9490s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18707717 bytes MEM: Free's : 27 free's of 18707717 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_129] | 1 | True | 15.31 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4128s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4142s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18830205 bytes MEM: Free's : 27 free's of 18830205 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_438] | 1 | True | 10.53 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.603s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10154s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10182s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21853869 bytes MEM: Free's : 26 free's of 21853869 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_346] | 1 | True | 12.92 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.481s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5864s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5888s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682381 bytes MEM: Free's : 26 free's of 18682381 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_149] | 1 | True | 20.90 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.248s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3339s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3349s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682333 bytes MEM: Free's : 26 free's of 18682333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_384] | 1 | True | 19.20 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8887s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8916s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20014929 bytes MEM: Free's : 27 free's of 20014929 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_168] | 1 | True | 22.72 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.269s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3521s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3532s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18778413 bytes MEM: Free's : 27 free's of 18778413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_96] | 1 | True | 17.07 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.394s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3930s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3952s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681453 bytes MEM: Free's : 26 free's of 18681453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_219] | 1 | True | 16.33 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.267s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3571s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3583s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681781 bytes MEM: Free's : 26 free's of 18681781 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_72] | 1 | True | 17.63 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8776s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8804s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682061 bytes MEM: Free's : 26 free's of 18682061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_212] | 1 | True | 9.66 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3707s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3720s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19116905 bytes MEM: Free's : 27 free's of 19116905 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_249] | 1 | True | 10.49 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.506s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9064s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9092s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18763613 bytes MEM: Free's : 27 free's of 18763613 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_298] | 1 | True | 13.28 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.461s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10369s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18820553 bytes MEM: Free's : 27 free's of 18820553 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_89] | 1 | True | 11.31 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.444s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5954s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5982s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18979629 bytes MEM: Free's : 27 free's of 18979629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_292] | 1 | True | 12.72 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1019s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8372s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18799161 bytes MEM: Free's : 26 free's of 18799161 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_385] | 1 | True | 22.44 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.392s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6677s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6709s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20014929 bytes MEM: Free's : 27 free's of 20014929 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_247] | 1 | True | 14.75 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3998s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4010s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731053 bytes MEM: Free's : 26 free's of 18731053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_336] | 1 | True | 13.30 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7682s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7714s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18916269 bytes MEM: Free's : 26 free's of 18916269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_51] | 1 | True | 11.04 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.384s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2648s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2657s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 22097813 bytes MEM: Free's : 27 free's of 22097813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_277] | 1 | True | 10.19 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.356s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4427s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4439s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18688413 bytes MEM: Free's : 26 free's of 18688413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_31] | 1 | True | 12.55 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.260s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2798s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2811s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58526637 bytes MEM: Free's : 26 free's of 58526637 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_179] | 1 | True | 11.07 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.463s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7937s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7954s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19014669 bytes MEM: Free's : 27 free's of 19014669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_329] | 1 | True | 18.13 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8916s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8942s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18742689 bytes MEM: Free's : 27 free's of 18742689 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_81] | 1 | True | 21.43 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.559s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9561s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9588s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18716973 bytes MEM: Free's : 27 free's of 18716973 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_232] | 1 | True | 10.42 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.247s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4155s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4168s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18684237 bytes MEM: Free's : 26 free's of 18684237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_373] | 1 | True | 15.94 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3156s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3169s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18783309 bytes MEM: Free's : 27 free's of 18783309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_63] | 0 | - | 0.29 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------------------------------------------------- | Div | /Div | Layer /Div - op type Div, number of input dims(7) is not supported by TIDL, maximum dimension allowed is 6 | --------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_248] | 1 | True | 15.17 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.361s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4371s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4385s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18749597 bytes MEM: Free's : 27 free's of 18749597 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_148] | 1 | True | 14.75 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3726s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3741s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682333 bytes MEM: Free's : 26 free's of 18682333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_217] | 1 | True | 12.40 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.438s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4287s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4303s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699525 bytes MEM: Free's : 27 free's of 18699525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_11] | 1 | True | 15.80 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.353s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4668s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4688s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18842401 bytes MEM: Free's : 27 free's of 18842401 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_296] | 1 | True | 15.55 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.461s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7338s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7371s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18817673 bytes MEM: Free's : 27 free's of 18817673 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_252] | 1 | True | 12.28 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.275s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3055s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3066s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18897209 bytes MEM: Free's : 27 free's of 18897209 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_253] | 1 | True | 12.72 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.390s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3283s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3301s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18914221 bytes MEM: Free's : 26 free's of 18914221 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_436] | 1 | True | 21.98 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.516s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9247s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9278s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 22180689 bytes MEM: Free's : 27 free's of 22180689 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_353] | 1 | True | 18.00 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7161s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18686269 bytes MEM: Free's : 26 free's of 18686269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_191] | 1 | True | 13.49 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.369s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4266s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4284s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699353 bytes MEM: Free's : 27 free's of 18699353 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_260] | 1 | True | 15.88 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.359s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4090s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4109s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19488569 bytes MEM: Free's : 27 free's of 19488569 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_410] | 1 | True | 19.84 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.570s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8127s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8154s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730573 bytes MEM: Free's : 26 free's of 18730573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_128] | 1 | True | 15.59 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.35s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.565s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9883s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9915s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18836397 bytes MEM: Free's : 26 free's of 18836397 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_293] | 1 | True | 9.87 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6594s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6610s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18818105 bytes MEM: Free's : 27 free's of 18818105 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_379] | 1 | True | 19.66 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.515s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7957s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7985s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19008597 bytes MEM: Free's : 26 free's of 19008597 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_421] | 1 | True | 22.43 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8285s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8308s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18878225 bytes MEM: Free's : 26 free's of 18878225 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_339] | 1 | True | 9.64 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.263s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3640s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3651s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19380909 bytes MEM: Free's : 26 free's of 19380909 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_24] | 1 | True | 15.05 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 0 | ------------------------------------------------------------------------------ Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3253s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3264s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18764253 bytes MEM: Free's : 26 free's of 18764253 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_318] | 1 | True | 16.51 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.35s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.495s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6981s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7008s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681605 bytes MEM: Free's : 26 free's of 18681605 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_388] | 1 | True | 14.62 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.49s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.50s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.561s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9514s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9536s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20018829 bytes MEM: Free's : 27 free's of 20018829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_359] | 1 | True | 19.81 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8428s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8443s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18719649 bytes MEM: Free's : 27 free's of 18719649 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_344] | 1 | True | 19.38 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.441s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6809s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6835s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682213 bytes MEM: Free's : 26 free's of 18682213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_326] | 1 | True | 20.01 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.495s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8138s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8165s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692173 bytes MEM: Free's : 26 free's of 18692173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_381] | 1 | True | 15.88 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.361s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4660s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4673s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19012269 bytes MEM: Free's : 26 free's of 19012269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_32] | 1 | True | 14.37 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5615s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5629s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24640429 bytes MEM: Free's : 26 free's of 24640429 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_120] | 1 | True | 11.57 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.543s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10258s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10285s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18740013 bytes MEM: Free's : 27 free's of 18740013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_306] | 1 | True | 19.97 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.544s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10011s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10049s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19178441 bytes MEM: Free's : 27 free's of 19178441 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_420] | 1 | True | 16.57 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.39s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.42s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.494s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8493s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8525s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18893229 bytes MEM: Free's : 26 free's of 18893229 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_243] | 1 | True | 13.69 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.256s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2606s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2616s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18748985 bytes MEM: Free's : 27 free's of 18748985 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_347] | 1 | True | 12.93 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3408s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3424s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682213 bytes MEM: Free's : 26 free's of 18682213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_178] | 1 | True | 10.04 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.567s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8884s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8917s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19047213 bytes MEM: Free's : 27 free's of 19047213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_25] | 1 | True | 10.47 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3132s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3145s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19747813 bytes MEM: Free's : 27 free's of 19747813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_192] | 1 | True | 18.68 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.449s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4707s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4723s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681353 bytes MEM: Free's : 26 free's of 18681353 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_316] | 1 | True | 13.14 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.520s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14747s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14775s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699441 bytes MEM: Free's : 27 free's of 18699441 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_414] | 1 | True | 13.10 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.414s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6589s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6607s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18751169 bytes MEM: Free's : 27 free's of 18751169 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_47] | 1 | True | 13.99 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.891s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8330s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8353s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 141382493 bytes MEM: Free's : 27 free's of 141382493 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_168] | 1 | True | 20.20 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.509s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6712s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6723s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18759981 bytes MEM: Free's : 26 free's of 18759981 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_33] | 1 | True | 16.91 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.387s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5978s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6000s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22957933 bytes MEM: Free's : 26 free's of 22957933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_425] | 1 | True | 13.71 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 0 | ------------------------------------------------------------------------------ Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.370s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4288s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4296s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19456633 bytes MEM: Free's : 26 free's of 19456633 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_75] | 1 | True | 14.36 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.562s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8075s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8105s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18703437 bytes MEM: Free's : 27 free's of 18703437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_313] | 1 | True | 15.84 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.465s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8385s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8409s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20603849 bytes MEM: Free's : 27 free's of 20603849 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_58] | 1 | True | 23.44 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6842s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6861s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 218958765 bytes MEM: Free's : 26 free's of 218958765 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_275] | 1 | True | 15.85 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.379s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5244s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5260s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18701609 bytes MEM: Free's : 27 free's of 18701609 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_332] | 1 | True | 21.58 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.458s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9527s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9554s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18757969 bytes MEM: Free's : 27 free's of 18757969 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_396] | 1 | True | 20.92 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3329s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3344s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18684205 bytes MEM: Free's : 26 free's of 18684205 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_131] | 1 | True | 10.08 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10283s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10311s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18813357 bytes MEM: Free's : 26 free's of 18813357 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_58] | 1 | True | 16.97 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7355s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7382s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 202200261 bytes MEM: Free's : 27 free's of 202200261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_77] | 1 | True | 11.17 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8058s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8083s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18685293 bytes MEM: Free's : 26 free's of 18685293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_61] | 0 | - | 0.30 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------------------------------------------------- | Div | /Div | Layer /Div - op type Div, number of input dims(7) is not supported by TIDL, maximum dimension allowed is 6 | --------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_67] | 1 | True | 9.29 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.287s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4766s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4780s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681237 bytes MEM: Free's : 26 free's of 18681237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_204] | 1 | True | 9.69 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5755s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5767s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18707001 bytes MEM: Free's : 26 free's of 18707001 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_347] | 1 | True | 18.84 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.252s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3338s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3351s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700585 bytes MEM: Free's : 27 free's of 18700585 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_216] | 1 | True | 17.23 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.320s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3731s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3744s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699453 bytes MEM: Free's : 27 free's of 18699453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_407] | 1 | True | 13.78 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.651s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8795s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8839s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18712961 bytes MEM: Free's : 27 free's of 18712961 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_60] | 1 | True | 17.32 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.221s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2421s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2432s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 162468845 bytes MEM: Free's : 27 free's of 162468845 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_341] | 1 | True | 13.91 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2871s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2885s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681293 bytes MEM: Free's : 26 free's of 18681293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_260] | 1 | True | 15.70 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.281s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3512s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3527s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19469485 bytes MEM: Free's : 26 free's of 19469485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_375] | 1 | True | 12.50 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.511s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9025s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9046s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19026849 bytes MEM: Free's : 27 free's of 19026849 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_102] | 1 | True | 20.59 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.547s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.11500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.11672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14709s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14734s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18701229 bytes MEM: Free's : 27 free's of 18701229 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_171] | 1 | True | 11.62 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.392s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6166s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6183s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18759765 bytes MEM: Free's : 26 free's of 18759765 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_81] | 1 | True | 18.14 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.226s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.228s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.672s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9896s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9924s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18698541 bytes MEM: Free's : 26 free's of 18698541 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_251] | 1 | True | 16.93 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.511s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9504s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9532s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18878509 bytes MEM: Free's : 26 free's of 18878509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_147] | 1 | True | 10.20 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.532s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8666s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8693s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682165 bytes MEM: Free's : 26 free's of 18682165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_163] | 1 | True | 19.51 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.286s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3964s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3978s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18700629 bytes MEM: Free's : 26 free's of 18700629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_318] | 1 | True | 9.55 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.467s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8229s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8258s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699937 bytes MEM: Free's : 27 free's of 18699937 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_240] | 1 | True | 15.75 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.472s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13950s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13975s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693613 bytes MEM: Free's : 26 free's of 18693613 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_49] | 1 | True | 26.56 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.438s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5157s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5173s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 157092781 bytes MEM: Free's : 26 free's of 157092781 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_337] | 1 | True | 17.25 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8243s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8272s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19395489 bytes MEM: Free's : 27 free's of 19395489 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_108] | 1 | True | 12.26 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.515s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8332s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8368s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18701765 bytes MEM: Free's : 27 free's of 18701765 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_261] | 1 | True | 11.07 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4648s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4666s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19614637 bytes MEM: Free's : 26 free's of 19614637 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_279] | 1 | True | 21.77 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.568s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9205s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9246s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18688813 bytes MEM: Free's : 26 free's of 18688813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_228] | 1 | True | 10.76 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3228s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3241s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18702393 bytes MEM: Free's : 27 free's of 18702393 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_90] | 1 | True | 20.97 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.292s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6130s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6144s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19057581 bytes MEM: Free's : 26 free's of 19057581 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_121] | 1 | True | 15.18 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5345s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5364s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18713661 bytes MEM: Free's : 26 free's of 18713661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_312] | 1 | True | 20.49 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.531s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8042s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8066s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20573289 bytes MEM: Free's : 26 free's of 20573289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_214] | 1 | True | 10.03 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.448s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6204s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6226s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19100845 bytes MEM: Free's : 26 free's of 19100845 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_162] | 1 | True | 9.60 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.591s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11884s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11914s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18720813 bytes MEM: Free's : 27 free's of 18720813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_427] | 1 | True | 10.19 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.491s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8085s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8116s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19471149 bytes MEM: Free's : 26 free's of 19471149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_136] | 1 | True | 15.91 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6713s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6745s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19303341 bytes MEM: Free's : 26 free's of 19303341 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_164] | 1 | True | 9.33 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9436s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9459s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701421 bytes MEM: Free's : 26 free's of 18701421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_281] | 1 | True | 18.27 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.395s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6025s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6050s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18688989 bytes MEM: Free's : 26 free's of 18688989 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_116] | 1 | True | 19.25 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.449s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7135s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7156s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692013 bytes MEM: Free's : 26 free's of 18692013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_351] | 1 | True | 18.20 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4169s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4181s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18686081 bytes MEM: Free's : 26 free's of 18686081 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_280] | 1 | True | 10.18 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.352s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4599s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4615s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18706889 bytes MEM: Free's : 27 free's of 18706889 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_75] | 1 | True | 21.39 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8239s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8265s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18685237 bytes MEM: Free's : 26 free's of 18685237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_37] | 1 | True | 10.32 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6338s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6360s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 23538613 bytes MEM: Free's : 27 free's of 23538613 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_167] | 1 | True | 13.49 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3506s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3524s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18777933 bytes MEM: Free's : 27 free's of 18777933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_3] | 1 | True | 12.49 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.555s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9415s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9444s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18702497 bytes MEM: Free's : 27 free's of 18702497 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_142] | 1 | True | 11.67 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.450s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6868s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6888s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699853 bytes MEM: Free's : 27 free's of 18699853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_111] | 1 | True | 15.13 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4109s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4124s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18707501 bytes MEM: Free's : 27 free's of 18707501 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_399] | 1 | True | 10.98 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.506s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9358s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9388s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18684581 bytes MEM: Free's : 26 free's of 18684581 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_16] | 1 | True | 18.98 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5082s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5094s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26819501 bytes MEM: Free's : 26 free's of 26819501 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_251] | 1 | True | 15.18 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5082s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5095s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18897209 bytes MEM: Free's : 27 free's of 18897209 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_376] | 1 | True | 22.21 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.431s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7992s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8014s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19029329 bytes MEM: Free's : 27 free's of 19029329 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_368] | 1 | True | 19.96 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5079s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5095s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18782289 bytes MEM: Free's : 27 free's of 18782289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_288] | 1 | True | 15.03 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4154s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4168s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18728969 bytes MEM: Free's : 27 free's of 18728969 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_191] | 1 | True | 20.12 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.561s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9081s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9114s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681125 bytes MEM: Free's : 26 free's of 18681125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_415] | 1 | True | 19.33 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.35s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.37s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.574s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9952s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10012s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18732493 bytes MEM: Free's : 26 free's of 18732493 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_389] | 1 | True | 10.55 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.347s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4284s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4299s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20018829 bytes MEM: Free's : 27 free's of 20018829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_20] | 1 | True | 16.87 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.511s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6812s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6837s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18777181 bytes MEM: Free's : 26 free's of 18777181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_30] | 1 | True | 10.27 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.519s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9251s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9280s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 52259757 bytes MEM: Free's : 26 free's of 52259757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_331] | 1 | True | 21.28 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.549s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9370s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9393s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18725229 bytes MEM: Free's : 26 free's of 18725229 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_257] | 1 | True | 9.25 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3842s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3855s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18957149 bytes MEM: Free's : 27 free's of 18957149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_206] | 1 | True | 14.54 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.459s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7606s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7631s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18725945 bytes MEM: Free's : 27 free's of 18725945 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_440] | 1 | True | 13.01 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.419s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5811s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5837s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23063469 bytes MEM: Free's : 26 free's of 23063469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_302] | 1 | True | 15.58 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.277s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3012s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3022s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19173689 bytes MEM: Free's : 27 free's of 19173689 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_403] | 1 | True | 12.83 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3568s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3587s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693437 bytes MEM: Free's : 26 free's of 18693437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_278] | 1 | True | 16.95 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5514s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5534s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18706745 bytes MEM: Free's : 27 free's of 18706745 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_132] | 1 | True | 12.07 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2928s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2944s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18860973 bytes MEM: Free's : 26 free's of 18860973 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_365] | 1 | True | 13.31 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.562s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4181s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4192s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18720749 bytes MEM: Free's : 27 free's of 18720749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_99] | 1 | True | 17.46 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.525s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8675s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8702s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699733 bytes MEM: Free's : 27 free's of 18699733 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_382] | 1 | True | 22.24 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.589s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10659s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10694s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19131309 bytes MEM: Free's : 26 free's of 19131309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_78] | 1 | True | 16.44 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7571s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7595s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18686637 bytes MEM: Free's : 26 free's of 18686637 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_145] | 1 | True | 16.86 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.512s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8751s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8785s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700365 bytes MEM: Free's : 27 free's of 18700365 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_22] | 1 | True | 9.41 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2710s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2722s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18805561 bytes MEM: Free's : 27 free's of 18805561 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_324] | 1 | True | 10.22 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.407s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6485s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6505s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18684461 bytes MEM: Free's : 26 free's of 18684461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_266] | 1 | True | 13.88 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.542s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10976s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11009s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699717 bytes MEM: Free's : 27 free's of 18699717 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_103] | 1 | True | 13.43 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.507s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8935s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8962s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682957 bytes MEM: Free's : 26 free's of 18682957 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_182] | 1 | True | 9.41 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3855s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3864s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19119021 bytes MEM: Free's : 26 free's of 19119021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_64] | 0 | - | 0.36 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------------------------------------------------- | Div | /Div | Layer /Div - op type Div, number of input dims(7) is not supported by TIDL, maximum dimension allowed is 6 | --------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_436] | 1 | True | 23.67 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.39s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.40s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6830s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6853s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22080429 bytes MEM: Free's : 26 free's of 22080429 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_245] | 1 | True | 19.73 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.429s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5362s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5382s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18760505 bytes MEM: Free's : 27 free's of 18760505 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_325] | 1 | True | 13.85 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.572s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11344s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11370s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18710049 bytes MEM: Free's : 27 free's of 18710049 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_300] | 1 | True | 15.35 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7766s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7789s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19172201 bytes MEM: Free's : 27 free's of 19172201 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_322] | 1 | True | 20.09 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7828s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7847s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18702161 bytes MEM: Free's : 27 free's of 18702161 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_36] | 1 | True | 12.67 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.362s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4274s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4291s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 23077109 bytes MEM: Free's : 27 free's of 23077109 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_254] | 1 | True | 17.37 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.466s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9193s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9220s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18877509 bytes MEM: Free's : 26 free's of 18877509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_394] | 1 | True | 17.58 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3900s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3911s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18702369 bytes MEM: Free's : 27 free's of 18702369 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_87] | 1 | True | 17.44 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8911s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8930s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18959413 bytes MEM: Free's : 26 free's of 18959413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_377] | 1 | True | 13.34 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.519s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8649s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8673s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19010349 bytes MEM: Free's : 26 free's of 19010349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_111] | 1 | True | 16.38 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.526s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9353s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9381s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18689133 bytes MEM: Free's : 26 free's of 18689133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_94] | 1 | True | 19.44 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.507s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7913s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7940s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699661 bytes MEM: Free's : 27 free's of 18699661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_208] | 1 | True | 10.95 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4016s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4031s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18785337 bytes MEM: Free's : 26 free's of 18785337 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_1] | 1 | True | 15.46 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.524s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4595s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4608s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18686637 bytes MEM: Free's : 26 free's of 18686637 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_354] | 1 | True | 10.99 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2916s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2926s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18686893 bytes MEM: Free's : 26 free's of 18686893 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_236] | 1 | True | 15.58 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.448s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7908s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7930s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693389 bytes MEM: Free's : 26 free's of 18693389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_232] | 1 | True | 13.98 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.397s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6847s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6868s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18702573 bytes MEM: Free's : 27 free's of 18702573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_362] | 1 | True | 18.02 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8480s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8507s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18705069 bytes MEM: Free's : 26 free's of 18705069 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_46] | 1 | True | 14.60 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.274s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6085s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6099s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 131926957 bytes MEM: Free's : 26 free's of 131926957 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_71] | 1 | True | 10.02 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.562s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10236s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10263s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682037 bytes MEM: Free's : 26 free's of 18682037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_8] | 1 | True | 15.40 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2417s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2423s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18714029 bytes MEM: Free's : 26 free's of 18714029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_367] | 1 | True | 15.63 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.340s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5418s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5432s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18762817 bytes MEM: Free's : 26 free's of 18762817 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_321] | 1 | True | 23.14 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5958s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5978s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18683649 bytes MEM: Free's : 26 free's of 18683649 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_39] | 1 | True | 12.87 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.320s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4088s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4104s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 23061557 bytes MEM: Free's : 27 free's of 23061557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_283] | 1 | True | 9.12 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4341s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4360s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18708809 bytes MEM: Free's : 27 free's of 18708809 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_206] | 1 | True | 15.45 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4191s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4205s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18707437 bytes MEM: Free's : 26 free's of 18707437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_38] | 1 | True | 18.98 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.803s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4179s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4196s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 23178833 bytes MEM: Free's : 27 free's of 23178833 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_376] | 1 | True | 13.89 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4072s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4089s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19010349 bytes MEM: Free's : 26 free's of 19010349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_94] | 1 | True | 11.41 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.437s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14711s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14735s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681437 bytes MEM: Free's : 26 free's of 18681437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_107] | 1 | True | 23.66 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.740s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8940s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8970s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682989 bytes MEM: Free's : 26 free's of 18682989 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_67] | 1 | True | 13.84 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.361s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5081s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5095s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699437 bytes MEM: Free's : 27 free's of 18699437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_370] | 1 | True | 16.56 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.443s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6570s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6589s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18778029 bytes MEM: Free's : 26 free's of 18778029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_282] | 1 | True | 15.45 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.517s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10498s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10526s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18688989 bytes MEM: Free's : 26 free's of 18688989 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_256] | 1 | True | 14.28 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3156s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3169s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18898397 bytes MEM: Free's : 27 free's of 18898397 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_148] | 1 | True | 12.36 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6350s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6375s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700653 bytes MEM: Free's : 27 free's of 18700653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_352] | 1 | True | 14.61 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4422s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4434s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18704593 bytes MEM: Free's : 27 free's of 18704593 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_76] | 1 | True | 17.74 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4041s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4058s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18685293 bytes MEM: Free's : 26 free's of 18685293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_406] | 1 | True | 17.77 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.357s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4369s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4384s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18694397 bytes MEM: Free's : 26 free's of 18694397 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_126] | 1 | True | 19.12 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.523s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10188s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10216s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18831149 bytes MEM: Free's : 27 free's of 18831149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_119] | 1 | True | 11.67 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3129s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3142s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18732333 bytes MEM: Free's : 27 free's of 18732333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_263] | 1 | True | 14.04 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.286s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2813s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2826s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19471789 bytes MEM: Free's : 26 free's of 19471789 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_173] | 1 | True | 11.91 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.370s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3738s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3748s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18761517 bytes MEM: Free's : 26 free's of 18761517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_174] | 1 | True | 11.65 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9596s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9626s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18790317 bytes MEM: Free's : 26 free's of 18790317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_304] | 1 | True | 18.50 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.349s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4499s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4514s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19172489 bytes MEM: Free's : 27 free's of 19172489 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_278] | 1 | True | 11.67 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3552s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3565s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18688413 bytes MEM: Free's : 26 free's of 18688413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_117] | 1 | True | 22.92 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9470s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9498s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18731853 bytes MEM: Free's : 27 free's of 18731853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_233] | 1 | True | 19.46 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.384s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5877s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5903s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18685037 bytes MEM: Free's : 26 free's of 18685037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_291] | 1 | True | 15.01 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4769s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4785s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18721837 bytes MEM: Free's : 26 free's of 18721837 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_160] | 1 | True | 16.28 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.424s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7973s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7993s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18700653 bytes MEM: Free's : 26 free's of 18700653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_140] | 1 | True | 10.53 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.565s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10040s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10069s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19387205 bytes MEM: Free's : 27 free's of 19387205 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_213] | 1 | True | 18.68 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.286s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4925s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4940s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19119929 bytes MEM: Free's : 27 free's of 19119929 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_208] | 1 | True | 11.87 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.425s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5934s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5960s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18803561 bytes MEM: Free's : 27 free's of 18803561 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_308] | 1 | True | 10.08 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3623s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3636s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20591465 bytes MEM: Free's : 27 free's of 20591465 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_146] | 1 | True | 20.68 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4730s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4749s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682157 bytes MEM: Free's : 26 free's of 18682157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_142] | 1 | True | 11.78 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.524s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8152s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8179s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681453 bytes MEM: Free's : 26 free's of 18681453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_112] | 1 | True | 16.47 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.463s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6872s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6891s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18690477 bytes MEM: Free's : 26 free's of 18690477 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_333] | 1 | True | 12.12 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.527s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8070s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8096s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18854977 bytes MEM: Free's : 26 free's of 18854977 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_127] | 1 | True | 14.32 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8706s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8730s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18831149 bytes MEM: Free's : 27 free's of 18831149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_311] | 1 | True | 22.43 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3350s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3362s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20720557 bytes MEM: Free's : 26 free's of 20720557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_45] | 1 | True | 11.60 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.362s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3974s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3984s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 43883437 bytes MEM: Free's : 26 free's of 43883437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_358] | 1 | True | 12.74 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.391s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6112s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6138s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18705933 bytes MEM: Free's : 27 free's of 18705933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_101] | 1 | True | 9.68 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 0 | ------------------------------------------------------------------------------ Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.360s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4362s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4379s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18669949 bytes MEM: Free's : 26 free's of 18669949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_234] | 1 | True | 17.05 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.437s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5744s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5765s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18711401 bytes MEM: Free's : 27 free's of 18711401 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_307] | 1 | True | 23.73 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.492s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8512s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8531s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19338157 bytes MEM: Free's : 26 free's of 19338157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_339] | 1 | True | 12.38 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2794s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2805s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19400529 bytes MEM: Free's : 27 free's of 19400529 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_96] | 1 | True | 13.18 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5919s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5939s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699725 bytes MEM: Free's : 27 free's of 18699725 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_427] | 1 | True | 19.66 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.531s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8625s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8650s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19490129 bytes MEM: Free's : 27 free's of 19490129 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_352] | 1 | True | 16.77 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.508s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9332s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9358s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18686269 bytes MEM: Free's : 26 free's of 18686269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_345] | 1 | True | 12.30 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.588s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9231s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9262s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682213 bytes MEM: Free's : 26 free's of 18682213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_14] | 1 | True | 15.59 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8329s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8355s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20718509 bytes MEM: Free's : 26 free's of 20718509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_237] | 1 | True | 20.88 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5455s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5470s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18695341 bytes MEM: Free's : 26 free's of 18695341 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_46] | 1 | True | 24.07 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.309s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3503s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3513s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 134042437 bytes MEM: Free's : 27 free's of 134042437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_44] | 1 | True | 11.40 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3558s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3572s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27331501 bytes MEM: Free's : 26 free's of 27331501 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_327] | 1 | True | 12.99 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.531s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6336s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6350s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692173 bytes MEM: Free's : 26 free's of 18692173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_104] | 1 | True | 15.00 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10041s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10070s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18701613 bytes MEM: Free's : 27 free's of 18701613 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_267] | 1 | True | 21.41 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.532s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9140s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9167s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681557 bytes MEM: Free's : 26 free's of 18681557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_405] | 1 | True | 18.80 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10728s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10765s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693457 bytes MEM: Free's : 26 free's of 18693457 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_288] | 1 | True | 12.58 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.544s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9800s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9832s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18710505 bytes MEM: Free's : 26 free's of 18710505 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_112] | 1 | True | 14.37 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.528s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8805s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8834s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18709293 bytes MEM: Free's : 27 free's of 18709293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_435] | 1 | True | 16.10 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.401s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7567s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7592s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21838509 bytes MEM: Free's : 26 free's of 21838509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_19] | 1 | True | 13.58 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4951s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4963s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18797989 bytes MEM: Free's : 27 free's of 18797989 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_231] | 1 | True | 13.65 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.491s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7305s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7329s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18684237 bytes MEM: Free's : 26 free's of 18684237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_257] | 1 | True | 9.67 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5695s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5720s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18951085 bytes MEM: Free's : 26 free's of 18951085 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_424] | 1 | True | 23.35 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3088s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3100s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18952769 bytes MEM: Free's : 27 free's of 18952769 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_141] | 1 | True | 16.31 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.287s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4816s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4828s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681389 bytes MEM: Free's : 26 free's of 18681389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_269] | 1 | True | 10.01 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.520s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9989s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10029s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18701033 bytes MEM: Free's : 27 free's of 18701033 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_332] | 1 | True | 12.11 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2841s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2856s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18739629 bytes MEM: Free's : 26 free's of 18739629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_40] | 1 | True | 12.23 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8204s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8223s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 22963049 bytes MEM: Free's : 27 free's of 22963049 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_124] | 1 | True | 16.51 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3953s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3966s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18742085 bytes MEM: Free's : 27 free's of 18742085 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_56] | 1 | True | 17.27 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.374s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5020s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5035s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 27735237 bytes MEM: Free's : 27 free's of 27735237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_97] | 1 | True | 11.10 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.50s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.51s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.553s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7337s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7363s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681437 bytes MEM: Free's : 26 free's of 18681437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_300] | 1 | True | 22.47 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.250s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3417s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3426s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19153977 bytes MEM: Free's : 26 free's of 19153977 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_400] | 1 | True | 21.00 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.668s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9557s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9590s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18703329 bytes MEM: Free's : 27 free's of 18703329 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_117] | 1 | True | 12.11 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 0 | ------------------------------------------------------------------------------ Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3920s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3937s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18700669 bytes MEM: Free's : 26 free's of 18700669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_4] | 1 | True | 11.15 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5918s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5933s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18689645 bytes MEM: Free's : 26 free's of 18689645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_224] | 1 | True | 10.21 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4378s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4397s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681805 bytes MEM: Free's : 26 free's of 18681805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_351] | 1 | True | 17.88 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5413s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5437s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18704353 bytes MEM: Free's : 27 free's of 18704353 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_207] | 1 | True | 12.37 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.610s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11738s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11763s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18734393 bytes MEM: Free's : 27 free's of 18734393 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_124] | 1 | True | 9.95 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.267s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4503s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4524s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18725805 bytes MEM: Free's : 26 free's of 18725805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_181] | 1 | True | 13.86 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4117s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4133s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19018637 bytes MEM: Free's : 27 free's of 19018637 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_433] | 1 | True | 14.08 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 0 | ------------------------------------------------------------------------------ Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.510s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6832s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6861s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21822073 bytes MEM: Free's : 26 free's of 21822073 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_56] | 1 | True | 19.62 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6687s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6710s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 27714477 bytes MEM: Free's : 26 free's of 27714477 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_29] | 1 | True | 16.04 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.489s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8389s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8419s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 29184813 bytes MEM: Free's : 27 free's of 29184813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_118] | 1 | True | 10.36 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8117s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8142s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18732333 bytes MEM: Free's : 27 free's of 18732333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_40] | 1 | True | 14.82 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.270s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3034s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3045s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22944825 bytes MEM: Free's : 26 free's of 22944825 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_235] | 1 | True | 17.39 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.528s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8532s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8558s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18711737 bytes MEM: Free's : 27 free's of 18711737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_285] | 1 | True | 15.32 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.460s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5955s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5967s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18710669 bytes MEM: Free's : 26 free's of 18710669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_270] | 1 | True | 19.92 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.364s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4731s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4750s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682773 bytes MEM: Free's : 26 free's of 18682773 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_230] | 1 | True | 16.96 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.292s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3193s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3206s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18684037 bytes MEM: Free's : 26 free's of 18684037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_185] | 1 | True | 18.48 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4998s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5010s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19962669 bytes MEM: Free's : 27 free's of 19962669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_171] | 1 | True | 10.57 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4034s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4053s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18778125 bytes MEM: Free's : 27 free's of 18778125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_100] | 1 | True | 13.55 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.358s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6218s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6237s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681485 bytes MEM: Free's : 26 free's of 18681485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_106] | 1 | True | 10.48 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.347s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4647s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4661s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18701349 bytes MEM: Free's : 27 free's of 18701349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_287] | 1 | True | 22.28 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9315s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9338s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18731705 bytes MEM: Free's : 27 free's of 18731705 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_419] | 1 | True | 9.33 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3424s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3448s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18878829 bytes MEM: Free's : 26 free's of 18878829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_196] | 1 | True | 21.01 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.454s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8448s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8474s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682617 bytes MEM: Free's : 26 free's of 18682617 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_33] | 1 | True | 19.73 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.286s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3140s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3152s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 22977233 bytes MEM: Free's : 27 free's of 22977233 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_333] | 1 | True | 20.51 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.345s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3652s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3662s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18873249 bytes MEM: Free's : 27 free's of 18873249 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_193] | 1 | True | 20.49 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5146s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5165s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681365 bytes MEM: Free's : 26 free's of 18681365 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_69] | 1 | True | 13.38 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5136s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5157s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699469 bytes MEM: Free's : 27 free's of 18699469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_180] | 1 | True | 18.59 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8344s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8373s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19018637 bytes MEM: Free's : 27 free's of 19018637 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_273] | 1 | True | 16.52 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.533s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8863s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8887s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682997 bytes MEM: Free's : 26 free's of 18682997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_315] | 1 | True | 14.71 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6647s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6675s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21310381 bytes MEM: Free's : 26 free's of 21310381 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_49] | 1 | True | 18.68 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7686s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7706s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 150819749 bytes MEM: Free's : 27 free's of 150819749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_242] | 1 | True | 17.48 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.237s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3238s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3248s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730041 bytes MEM: Free's : 26 free's of 18730041 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_158] | 1 | True | 16.20 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.350s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6077s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6094s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18705549 bytes MEM: Free's : 27 free's of 18705549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_404] | 1 | True | 10.28 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.37s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.520s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6491s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6517s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18694061 bytes MEM: Free's : 26 free's of 18694061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_165] | 1 | True | 14.33 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4447s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4466s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18719885 bytes MEM: Free's : 27 free's of 18719885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_425] | 1 | True | 12.26 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6330s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6345s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19487649 bytes MEM: Free's : 27 free's of 19487649 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_426] | 1 | True | 9.61 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.531s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5218s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5236s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19471149 bytes MEM: Free's : 26 free's of 19471149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_330] | 1 | True | 10.84 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4059s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4072s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18725229 bytes MEM: Free's : 26 free's of 18725229 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_209] | 1 | True | 23.64 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.367s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4131s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4147s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18786349 bytes MEM: Free's : 26 free's of 18786349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_34] | 1 | True | 9.16 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.265s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2421s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2426s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 22969397 bytes MEM: Free's : 27 free's of 22969397 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_262] | 1 | True | 11.86 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.292s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3268s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3279s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19485617 bytes MEM: Free's : 27 free's of 19485617 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_431] | 1 | True | 16.11 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.571s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10154s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10180s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19478829 bytes MEM: Free's : 26 free's of 19478829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_412] | 1 | True | 15.86 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5341s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5355s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18733869 bytes MEM: Free's : 26 free's of 18733869 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_417] | 1 | True | 15.77 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 0 | ------------------------------------------------------------------------------ Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4183s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4201s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18865273 bytes MEM: Free's : 26 free's of 18865273 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_294] | 1 | True | 13.47 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.542s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5710s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5726s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18799597 bytes MEM: Free's : 26 free's of 18799597 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_80] | 1 | True | 8.94 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3772s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3786s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18716973 bytes MEM: Free's : 27 free's of 18716973 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_315] | 1 | True | 14.96 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.500s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8338s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8355s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 21132233 bytes MEM: Free's : 27 free's of 21132233 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_65] | 0 | - | 0.30 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------------------------------------------------- | Div | /Div | Layer /Div - op type Div, number of input dims(7) is not supported by TIDL, maximum dimension allowed is 6 | --------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_240] | 1 | True | 20.21 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.489s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8034s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8057s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18712061 bytes MEM: Free's : 27 free's of 18712061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_378] | 1 | True | 20.01 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.489s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9230s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9262s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19069869 bytes MEM: Free's : 26 free's of 19069869 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_137] | 1 | True | 14.09 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7699s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7721s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19205181 bytes MEM: Free's : 26 free's of 19205181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_60] | 1 | True | 13.02 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.552s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8953s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8986s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 162446253 bytes MEM: Free's : 26 free's of 162446253 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_166] | 1 | True | 12.50 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.507s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9054s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9077s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18708141 bytes MEM: Free's : 26 free's of 18708141 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_291] | 1 | True | 18.01 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.538s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9193s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9224s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18737225 bytes MEM: Free's : 27 free's of 18737225 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_255] | 1 | True | 15.75 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.465s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7846s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7873s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18879661 bytes MEM: Free's : 26 free's of 18879661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_176] | 1 | True | 10.54 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.354s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4255s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4272s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18996909 bytes MEM: Free's : 26 free's of 18996909 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_102] | 1 | True | 12.69 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5055s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5074s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682957 bytes MEM: Free's : 26 free's of 18682957 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_4] | 1 | True | 18.47 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.278s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3681s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3695s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18708001 bytes MEM: Free's : 27 free's of 18708001 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_76] | 1 | True | 17.83 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7972s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7994s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18703661 bytes MEM: Free's : 27 free's of 18703661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_366] | 1 | True | 18.62 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.35s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.418s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6218s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6232s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18708909 bytes MEM: Free's : 26 free's of 18708909 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_26] | 1 | True | 19.60 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.563s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9783s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9808s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26679213 bytes MEM: Free's : 26 free's of 26679213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_377] | 1 | True | 14.89 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4237s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4254s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19029329 bytes MEM: Free's : 27 free's of 19029329 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_54] | 1 | True | 15.24 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4037s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4051s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22047797 bytes MEM: Free's : 26 free's of 22047797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_153] | 1 | True | 10.77 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.376s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6459s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6480s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18704173 bytes MEM: Free's : 27 free's of 18704173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_13] | 1 | True | 14.94 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.490s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8857s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8883s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19207033 bytes MEM: Free's : 27 free's of 19207033 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_135] | 1 | True | 9.77 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3971s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3987s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19225389 bytes MEM: Free's : 27 free's of 19225389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_42] | 1 | True | 18.24 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.543s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11865s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11884s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19097765 bytes MEM: Free's : 27 free's of 19097765 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_384] | 1 | True | 15.85 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.354s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4485s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4504s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19995309 bytes MEM: Free's : 26 free's of 19995309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_141] | 1 | True | 13.16 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.525s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6510s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6538s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699605 bytes MEM: Free's : 27 free's of 18699605 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_242] | 1 | True | 13.82 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5383s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5400s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18748265 bytes MEM: Free's : 27 free's of 18748265 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_18] | 1 | True | 14.12 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8731s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8757s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18797989 bytes MEM: Free's : 27 free's of 18797989 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_353] | 1 | True | 15.50 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.381s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4159s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4174s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18704593 bytes MEM: Free's : 27 free's of 18704593 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_349] | 1 | True | 22.48 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.500s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8246s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8274s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700725 bytes MEM: Free's : 27 free's of 18700725 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_314] | 1 | True | 14.22 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6222s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6231s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20584621 bytes MEM: Free's : 26 free's of 20584621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_151] | 1 | True | 21.15 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.467s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11439s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11471s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18685877 bytes MEM: Free's : 26 free's of 18685877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_374] | 1 | True | 17.66 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8391s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8422s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18806669 bytes MEM: Free's : 27 free's of 18806669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_172] | 1 | True | 16.95 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.578s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10494s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10522s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18780045 bytes MEM: Free's : 27 free's of 18780045 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_364] | 1 | True | 10.42 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3875s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3892s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18720749 bytes MEM: Free's : 27 free's of 18720749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_301] | 1 | True | 20.96 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4176s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4191s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19173689 bytes MEM: Free's : 27 free's of 19173689 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_218] | 1 | True | 13.55 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.407s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6661s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6689s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681769 bytes MEM: Free's : 26 free's of 18681769 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_177] | 1 | True | 16.25 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4637s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4653s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19015469 bytes MEM: Free's : 27 free's of 19015469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_189] | 1 | True | 11.33 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.557s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7083s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7104s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19968909 bytes MEM: Free's : 27 free's of 19968909 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_247] | 1 | True | 14.33 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.520s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8562s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8590s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18749597 bytes MEM: Free's : 27 free's of 18749597 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_83] | 1 | True | 14.54 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3296s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3308s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18768717 bytes MEM: Free's : 27 free's of 18768717 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_209] | 1 | True | 15.12 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3279s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3295s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18805049 bytes MEM: Free's : 27 free's of 18805049 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_122] | 1 | True | 22.01 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.350s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5399s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5414s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18732741 bytes MEM: Free's : 27 free's of 18732741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_375] | 1 | True | 17.74 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8232s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8260s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19008577 bytes MEM: Free's : 26 free's of 19008577 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_53] | 1 | True | 14.89 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7175s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7196s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 22181493 bytes MEM: Free's : 27 free's of 22181493 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_188] | 1 | True | 10.96 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.507s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8755s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8777s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19968909 bytes MEM: Free's : 27 free's of 19968909 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_276] | 1 | True | 10.96 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.309s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4366s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4379s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18706601 bytes MEM: Free's : 27 free's of 18706601 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_244] | 1 | True | 14.42 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.485s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8735s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8750s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730477 bytes MEM: Free's : 26 free's of 18730477 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_273] | 1 | True | 16.37 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6790s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6816s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18701465 bytes MEM: Free's : 27 free's of 18701465 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_143] | 1 | True | 20.54 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6154s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6166s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682133 bytes MEM: Free's : 26 free's of 18682133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_285] | 1 | True | 14.44 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.554s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11004s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11038s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18729017 bytes MEM: Free's : 27 free's of 18729017 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_410] | 1 | True | 9.12 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7484s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7511s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18749009 bytes MEM: Free's : 27 free's of 18749009 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_290] | 1 | True | 22.95 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.364s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4212s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4226s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18730313 bytes MEM: Free's : 27 free's of 18730313 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_283] | 1 | True | 17.74 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.280s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6734s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6747s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18691117 bytes MEM: Free's : 26 free's of 18691117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_3] | 1 | True | 12.23 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.363s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4299s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4314s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18684237 bytes MEM: Free's : 26 free's of 18684237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_50] | 1 | True | 20.65 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.359s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3728s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3745s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18878661 bytes MEM: Free's : 27 free's of 18878661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_106] | 1 | True | 13.42 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3960s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3975s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682989 bytes MEM: Free's : 26 free's of 18682989 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_159] | 1 | True | 11.29 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.362s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11605s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11627s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18718797 bytes MEM: Free's : 27 free's of 18718797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_404] | 1 | True | 11.21 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.510s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8253s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8277s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18712721 bytes MEM: Free's : 27 free's of 18712721 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_91] | 1 | True | 11.18 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 0 | ------------------------------------------------------------------------------ Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3862s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3876s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18668181 bytes MEM: Free's : 26 free's of 18668181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_258] | 1 | True | 16.08 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3670s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3686s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19485545 bytes MEM: Free's : 27 free's of 19485545 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_90] | 1 | True | 16.33 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4372s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4386s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19075885 bytes MEM: Free's : 27 free's of 19075885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_432] | 1 | True | 14.74 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3743s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3762s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19713089 bytes MEM: Free's : 27 free's of 19713089 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_266] | 1 | True | 9.20 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.252s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3285s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3296s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681477 bytes MEM: Free's : 26 free's of 18681477 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_274] | 1 | True | 9.44 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3262s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3276s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682997 bytes MEM: Free's : 26 free's of 18682997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_312] | 1 | True | 18.38 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.500s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9532s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9563s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20591753 bytes MEM: Free's : 27 free's of 20591753 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_110] | 1 | True | 12.44 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.348s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4120s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4140s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18707501 bytes MEM: Free's : 27 free's of 18707501 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_360] | 1 | True | 22.71 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.520s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6675s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6700s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18720209 bytes MEM: Free's : 27 free's of 18720209 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_87] | 1 | True | 18.24 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5474s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5486s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18977613 bytes MEM: Free's : 27 free's of 18977613 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_154] | 1 | True | 14.61 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.500s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7938s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7963s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18686125 bytes MEM: Free's : 26 free's of 18686125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_310] | 1 | True | 12.48 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6441s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6462s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20594489 bytes MEM: Free's : 27 free's of 20594489 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_24] | 1 | True | 17.71 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.566s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9260s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9293s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18795313 bytes MEM: Free's : 27 free's of 18795313 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_421] | 1 | True | 18.72 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7712s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7734s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18896769 bytes MEM: Free's : 27 free's of 18896769 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_386] | 1 | True | 14.44 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.448s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3855s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3871s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20337489 bytes MEM: Free's : 27 free's of 20337489 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_138] | 1 | True | 23.87 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.638s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12689s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12719s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19226949 bytes MEM: Free's : 27 free's of 19226949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_411] | 1 | True | 16.56 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.528s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10438s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10465s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730573 bytes MEM: Free's : 26 free's of 18730573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_422] | 1 | True | 10.34 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.562s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7911s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7927s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18882669 bytes MEM: Free's : 26 free's of 18882669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_290] | 1 | True | 15.97 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3514s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3529s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18711821 bytes MEM: Free's : 26 free's of 18711821 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_245] | 1 | True | 13.46 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3862s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3872s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18739117 bytes MEM: Free's : 26 free's of 18739117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_108] | 1 | True | 13.75 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9081s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9108s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18683565 bytes MEM: Free's : 26 free's of 18683565 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_364] | 1 | True | 21.13 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.36s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.42s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.528s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5794s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5823s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702189 bytes MEM: Free's : 26 free's of 18702189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_7] | 1 | True | 13.67 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.562s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10135s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10163s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20931361 bytes MEM: Free's : 27 free's of 20931361 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_86] | 1 | True | 23.15 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.510s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9611s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9643s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18793261 bytes MEM: Free's : 27 free's of 18793261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_254] | 1 | True | 15.56 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.337s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4216s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4231s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18895793 bytes MEM: Free's : 27 free's of 18895793 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_225] | 1 | True | 17.39 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.527s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8576s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8604s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700221 bytes MEM: Free's : 27 free's of 18700221 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_301] | 1 | True | 14.00 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.245s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2926s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2936s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19154989 bytes MEM: Free's : 26 free's of 19154989 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_84] | 1 | True | 11.07 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8130s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8160s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18769709 bytes MEM: Free's : 27 free's of 18769709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_234] | 1 | True | 21.40 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4320s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4336s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693177 bytes MEM: Free's : 26 free's of 18693177 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_146] | 1 | True | 23.50 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4512s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4528s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700429 bytes MEM: Free's : 27 free's of 18700429 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_129] | 1 | True | 11.23 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.274s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3126s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3140s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18811965 bytes MEM: Free's : 26 free's of 18811965 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_305] | 1 | True | 13.09 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.414s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6995s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7023s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19178441 bytes MEM: Free's : 27 free's of 19178441 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_2] | 1 | True | 14.39 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7983s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8003s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18684253 bytes MEM: Free's : 26 free's of 18684253 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_143] | 1 | True | 9.93 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.509s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8055s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8084s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700333 bytes MEM: Free's : 27 free's of 18700333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_218] | 1 | True | 16.93 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.542s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7628s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7660s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699993 bytes MEM: Free's : 27 free's of 18699993 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_15] | 1 | True | 12.24 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.283s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4926s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4941s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 26838853 bytes MEM: Free's : 27 free's of 26838853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_27] | 1 | True | 20.22 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.515s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8988s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9019s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19797933 bytes MEM: Free's : 26 free's of 19797933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_73] | 1 | True | 9.02 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.344s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4915s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4928s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700333 bytes MEM: Free's : 27 free's of 18700333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_246] | 1 | True | 23.25 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.551s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11790s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11822s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18748337 bytes MEM: Free's : 27 free's of 18748337 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_414] | 1 | True | 10.68 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4410s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4425s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18732493 bytes MEM: Free's : 26 free's of 18732493 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_133] | 1 | True | 13.79 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 0 | ------------------------------------------------------------------------------ Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.373s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5081s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5094s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19192189 bytes MEM: Free's : 26 free's of 19192189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_323] | 1 | True | 15.12 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.253s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3201s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3210s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18683837 bytes MEM: Free's : 26 free's of 18683837 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_35] | 1 | True | 14.18 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5136s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5154s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 22976309 bytes MEM: Free's : 27 free's of 22976309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_41] | 1 | True | 18.43 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.459s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6381s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6403s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 22962993 bytes MEM: Free's : 27 free's of 22962993 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_210] | 1 | True | 14.43 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8078s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8102s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18786349 bytes MEM: Free's : 26 free's of 18786349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_161] | 1 | True | 10.24 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.566s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7138s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7164s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18700653 bytes MEM: Free's : 26 free's of 18700653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_298] | 1 | True | 10.47 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.429s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7691s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7720s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18801901 bytes MEM: Free's : 26 free's of 18801901 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_409] | 1 | True | 20.34 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 0 | ------------------------------------------------------------------------------ Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8878s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8899s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18717433 bytes MEM: Free's : 26 free's of 18717433 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_199] | 1 | True | 10.61 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6451s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6478s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18683053 bytes MEM: Free's : 26 free's of 18683053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_83] | 1 | True | 11.90 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.198s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2859s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2869s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18750517 bytes MEM: Free's : 26 free's of 18750517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_212] | 1 | True | 12.27 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.261s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2827s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2841s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19098681 bytes MEM: Free's : 26 free's of 19098681 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_355] | 1 | True | 17.05 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5207s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5224s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18686101 bytes MEM: Free's : 26 free's of 18686101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_86] | 1 | True | 20.33 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.50s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.52s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8415s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8445s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18774957 bytes MEM: Free's : 26 free's of 18774957 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_224] | 1 | True | 16.25 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.435s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8041s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8072s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700149 bytes MEM: Free's : 27 free's of 18700149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_48] | 1 | True | 24.22 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.403s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6856s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6864s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 119448485 bytes MEM: Free's : 27 free's of 119448485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_150] | 1 | True | 13.69 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4255s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4274s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682541 bytes MEM: Free's : 26 free's of 18682541 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_136] | 1 | True | 17.85 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.530s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7387s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7408s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19354413 bytes MEM: Free's : 27 free's of 19354413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_63] | 0 | - | 0.38 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------------------------------------------------- | Div | /Div | Layer /Div - op type Div, number of input dims(7) is not supported by TIDL, maximum dimension allowed is 6 | --------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_182] | 1 | True | 11.98 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.320s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3692s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3710s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19104653 bytes MEM: Free's : 27 free's of 19104653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_192] | 1 | True | 9.87 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.534s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8891s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8919s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699577 bytes MEM: Free's : 27 free's of 18699577 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_163] | 1 | True | 11.34 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3056s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3060s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18718989 bytes MEM: Free's : 27 free's of 18718989 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_350] | 1 | True | 15.75 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3905s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3923s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682589 bytes MEM: Free's : 26 free's of 18682589 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_272] | 1 | True | 12.54 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4031s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4047s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682809 bytes MEM: Free's : 26 free's of 18682809 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_226] | 1 | True | 16.49 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4528s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4542s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18684025 bytes MEM: Free's : 26 free's of 18684025 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_133] | 1 | True | 18.99 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.352s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4295s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4329s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19223373 bytes MEM: Free's : 27 free's of 19223373 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_313] | 1 | True | 21.08 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.340s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4165s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20584621 bytes MEM: Free's : 26 free's of 20584621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_21] | 1 | True | 15.88 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4635s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4648s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18811717 bytes MEM: Free's : 27 free's of 18811717 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_62] | 0 | - | 0.35 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------------------------------------------------- | Div | /Div | Layer /Div - op type Div, number of input dims(7) is not supported by TIDL, maximum dimension allowed is 6 | --------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_284] | 1 | True | 12.81 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.490s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9138s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9163s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18728681 bytes MEM: Free's : 27 free's of 18728681 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_335] | 1 | True | 23.61 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8481s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8509s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18856749 bytes MEM: Free's : 26 free's of 18856749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_369] | 1 | True | 15.15 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3876s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3892s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18763629 bytes MEM: Free's : 26 free's of 18763629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_325] | 1 | True | 9.33 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4097s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4111s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18691777 bytes MEM: Free's : 26 free's of 18691777 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_186] | 1 | True | 11.59 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7649s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7673s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20040621 bytes MEM: Free's : 26 free's of 20040621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_220] | 1 | True | 12.66 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.361s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3115s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3128s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700041 bytes MEM: Free's : 27 free's of 18700041 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_85] | 1 | True | 14.31 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.511s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10397s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10423s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18769709 bytes MEM: Free's : 27 free's of 18769709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_183] | 1 | True | 10.21 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8268s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8292s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19960653 bytes MEM: Free's : 27 free's of 19960653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_55] | 1 | True | 22.40 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.352s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4413s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4427s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21810093 bytes MEM: Free's : 26 free's of 21810093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_385] | 1 | True | 8.93 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4993s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5009s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19995309 bytes MEM: Free's : 26 free's of 19995309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_187] | 1 | True | 21.52 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10630s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10686s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19960845 bytes MEM: Free's : 27 free's of 19960845 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_319] | 1 | True | 10.89 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.491s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6868s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6891s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681605 bytes MEM: Free's : 26 free's of 18681605 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_268] | 1 | True | 16.73 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3413s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3430s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700985 bytes MEM: Free's : 27 free's of 18700985 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_370] | 1 | True | 22.85 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9957s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9986s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18801489 bytes MEM: Free's : 27 free's of 18801489 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_166] | 1 | True | 16.20 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3645s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3663s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18724493 bytes MEM: Free's : 27 free's of 18724493 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_372] | 1 | True | 18.73 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.701s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10364s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10395s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18764589 bytes MEM: Free's : 26 free's of 18764589 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_438] | 1 | True | 12.03 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4703s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4718s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 21873729 bytes MEM: Free's : 27 free's of 21873729 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_379] | 1 | True | 11.13 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6075s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6091s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19026969 bytes MEM: Free's : 27 free's of 19026969 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_336] | 1 | True | 17.25 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6361s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6376s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18934609 bytes MEM: Free's : 27 free's of 18934609 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_64] | 0 | - | 0.32 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------------------------------------------------- | Div | /Div | Layer /Div - op type Div, number of input dims(7) is not supported by TIDL, maximum dimension allowed is 6 | --------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_241] | 1 | True | 10.57 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.485s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9003s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9031s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18715229 bytes MEM: Free's : 27 free's of 18715229 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_70] | 1 | True | 13.16 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.363s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5716s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5731s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699501 bytes MEM: Free's : 27 free's of 18699501 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_356] | 1 | True | 21.24 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.628s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11903s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11943s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18686477 bytes MEM: Free's : 26 free's of 18686477 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_161] | 1 | True | 19.45 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.514s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8414s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8444s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18719021 bytes MEM: Free's : 27 free's of 18719021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_12] | 1 | True | 10.88 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5234s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5251s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18826105 bytes MEM: Free's : 27 free's of 18826105 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_127] | 1 | True | 14.62 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.242s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2378s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2387s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18812589 bytes MEM: Free's : 26 free's of 18812589 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_435] | 1 | True | 15.67 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3930s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3941s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 21858129 bytes MEM: Free's : 27 free's of 21858129 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_281] | 1 | True | 11.16 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.281s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3592s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3609s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18707465 bytes MEM: Free's : 27 free's of 18707465 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_200] | 1 | True | 13.51 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.485s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8750s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8771s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18705641 bytes MEM: Free's : 27 free's of 18705641 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_417] | 1 | True | 10.14 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6635s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6656s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18896289 bytes MEM: Free's : 27 free's of 18896289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_350] | 1 | True | 23.79 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8293s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8330s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700845 bytes MEM: Free's : 27 free's of 18700845 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_362] | 1 | True | 14.59 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.540s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9100s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9131s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18724689 bytes MEM: Free's : 27 free's of 18724689 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_243] | 1 | True | 17.23 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4849s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4863s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730477 bytes MEM: Free's : 26 free's of 18730477 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_371] | 1 | True | 11.39 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.545s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8335s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8365s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18781209 bytes MEM: Free's : 27 free's of 18781209 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_309] | 1 | True | 18.69 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16362s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16383s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20575405 bytes MEM: Free's : 26 free's of 20575405 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_211] | 1 | True | 19.66 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8539s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8561s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18822061 bytes MEM: Free's : 26 free's of 18822061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_328] | 1 | True | 13.38 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.432s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5985s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6008s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18713809 bytes MEM: Free's : 27 free's of 18713809 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_157] | 1 | True | 22.91 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9225s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9269s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18686285 bytes MEM: Free's : 26 free's of 18686285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_73] | 1 | True | 12.24 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.623s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9197s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9224s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682061 bytes MEM: Free's : 26 free's of 18682061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_175] | 1 | True | 13.14 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8966s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8991s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18996277 bytes MEM: Free's : 26 free's of 18996277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_346] | 1 | True | 12.95 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3319s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3334s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700705 bytes MEM: Free's : 27 free's of 18700705 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_26] | 1 | True | 10.93 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4734s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4751s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 26698541 bytes MEM: Free's : 27 free's of 26698541 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_265] | 1 | True | 14.83 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3363s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3375s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19731293 bytes MEM: Free's : 27 free's of 19731293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_437] | 1 | True | 22.81 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.443s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7300s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7334s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21835025 bytes MEM: Free's : 26 free's of 21835025 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_334] | 1 | True | 12.96 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.461s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6144s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6168s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18875729 bytes MEM: Free's : 27 free's of 18875729 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_84] | 1 | True | 12.47 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.280s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2681s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2692s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18751149 bytes MEM: Free's : 26 free's of 18751149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_170] | 1 | True | 11.81 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.370s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3872s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3890s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18786093 bytes MEM: Free's : 27 free's of 18786093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_202] | 1 | True | 18.33 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.491s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8675s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8703s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18687629 bytes MEM: Free's : 26 free's of 18687629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_349] | 1 | True | 22.82 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.228s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2319s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2325s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682381 bytes MEM: Free's : 26 free's of 18682381 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_284] | 1 | True | 18.45 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.537s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9729s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9760s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18710457 bytes MEM: Free's : 26 free's of 18710457 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_120] | 1 | True | 20.15 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7230s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7246s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18719661 bytes MEM: Free's : 26 free's of 18719661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_150] | 1 | True | 17.09 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.278s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2725s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2739s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700749 bytes MEM: Free's : 27 free's of 18700749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_7] | 1 | True | 11.86 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.368s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4461s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4475s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20912045 bytes MEM: Free's : 26 free's of 20912045 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_137] | 1 | True | 17.41 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7578s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7599s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19223421 bytes MEM: Free's : 27 free's of 19223421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_368] | 1 | True | 18.79 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6161s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6175s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18763629 bytes MEM: Free's : 26 free's of 18763629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_5] | 1 | True | 12.66 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5765s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5789s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18734369 bytes MEM: Free's : 27 free's of 18734369 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_253] | 1 | True | 15.18 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.526s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8704s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8735s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18944825 bytes MEM: Free's : 27 free's of 18944825 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_408] | 1 | True | 9.03 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.512s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9293s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9322s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18715201 bytes MEM: Free's : 27 free's of 18715201 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_153] | 1 | True | 14.07 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.420s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7399s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7419s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18685901 bytes MEM: Free's : 26 free's of 18685901 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_231] | 1 | True | 13.00 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.458s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7879s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7900s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18702573 bytes MEM: Free's : 27 free's of 18702573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_21] | 1 | True | 10.51 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.424s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6153s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6169s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18789293 bytes MEM: Free's : 26 free's of 18789293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_139] | 1 | True | 9.91 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.464s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7681s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7711s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19208109 bytes MEM: Free's : 26 free's of 19208109 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_105] | 1 | True | 9.38 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.252s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3719s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3736s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682941 bytes MEM: Free's : 26 free's of 18682941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_181] | 1 | True | 18.75 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.355s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4709s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4727s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18999981 bytes MEM: Free's : 26 free's of 18999981 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_43] | 1 | True | 16.32 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.495s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10231s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10259s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20282789 bytes MEM: Free's : 27 free's of 20282789 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_195] | 1 | True | 9.70 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.508s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8355s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8370s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681389 bytes MEM: Free's : 26 free's of 18681389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_383] | 1 | True | 15.99 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.444s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6050s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6075s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19991617 bytes MEM: Free's : 26 free's of 19991617 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_125] | 1 | True | 14.22 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.368s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4662s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4679s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18830157 bytes MEM: Free's : 27 free's of 18830157 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_183] | 1 | True | 19.34 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.540s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10716s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10746s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19942453 bytes MEM: Free's : 26 free's of 19942453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_286] | 1 | True | 16.53 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3457s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3471s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18729017 bytes MEM: Free's : 27 free's of 18729017 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_42] | 1 | True | 17.16 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.492s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6483s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6516s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19078573 bytes MEM: Free's : 26 free's of 19078573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_395] | 1 | True | 18.96 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.36s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.561s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10000s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10033s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18702369 bytes MEM: Free's : 27 free's of 18702369 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_28] | 1 | True | 10.17 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.349s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5606s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5628s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 29709125 bytes MEM: Free's : 27 free's of 29709125 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_44] | 1 | True | 21.17 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.242s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10669s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10681s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 26956709 bytes MEM: Free's : 27 free's of 26956709 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_330] | 1 | True | 17.95 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2547s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2559s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18743889 bytes MEM: Free's : 27 free's of 18743889 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_324] | 1 | True | 18.11 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9159s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9177s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18702801 bytes MEM: Free's : 27 free's of 18702801 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_241] | 1 | True | 21.22 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7876s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7900s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18697645 bytes MEM: Free's : 26 free's of 18697645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_123] | 1 | True | 10.76 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4636s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4657s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18732741 bytes MEM: Free's : 27 free's of 18732741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_152] | 1 | True | 15.92 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.523s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9416s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9442s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18704173 bytes MEM: Free's : 27 free's of 18704173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_303] | 1 | True | 13.16 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.542s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9613s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9639s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19190701 bytes MEM: Free's : 26 free's of 19190701 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_95] | 1 | True | 19.93 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4681s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4699s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681437 bytes MEM: Free's : 26 free's of 18681437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_268] | 1 | True | 9.53 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.348s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3510s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3522s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682761 bytes MEM: Free's : 26 free's of 18682761 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_248] | 1 | True | 14.53 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.356s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4484s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4510s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18731053 bytes MEM: Free's : 26 free's of 18731053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_207] | 1 | True | 19.30 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8193s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8223s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18716077 bytes MEM: Free's : 26 free's of 18716077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_92] | 1 | True | 9.92 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3725s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3733s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699445 bytes MEM: Free's : 27 free's of 18699445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_139] | 1 | True | 19.76 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.466s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7324s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7345s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19226949 bytes MEM: Free's : 27 free's of 19226949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_8] | 1 | True | 18.05 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3599s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3609s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18730297 bytes MEM: Free's : 27 free's of 18730297 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_105] | 1 | True | 17.40 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3014s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3029s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18701181 bytes MEM: Free's : 27 free's of 18701181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_306] | 1 | True | 13.51 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.546s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7963s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7984s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19159597 bytes MEM: Free's : 26 free's of 19159597 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_428] | 1 | True | 9.40 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.437s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7734s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7762s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19530669 bytes MEM: Free's : 26 free's of 19530669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_387] | 1 | True | 9.32 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4244s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4256s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20010009 bytes MEM: Free's : 27 free's of 20010009 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_28] | 1 | True | 11.01 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.289s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4576s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4587s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30215085 bytes MEM: Free's : 26 free's of 30215085 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_238] | 1 | True | 16.20 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.511s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9222s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9258s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18711473 bytes MEM: Free's : 27 free's of 18711473 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_113] | 1 | True | 11.95 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.421s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7878s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7904s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18707325 bytes MEM: Free's : 27 free's of 18707325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_437] | 1 | True | 12.99 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.340s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4416s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4429s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 21853569 bytes MEM: Free's : 27 free's of 21853569 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_415] | 1 | True | 18.70 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3065s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3081s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18751169 bytes MEM: Free's : 27 free's of 18751169 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_35] | 1 | True | 14.31 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.352s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3867s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3885s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22951373 bytes MEM: Free's : 26 free's of 22951373 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_85] | 1 | True | 22.89 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.382s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5422s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5437s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18751149 bytes MEM: Free's : 26 free's of 18751149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_411] | 1 | True | 22.20 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.419s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6825s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6846s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18749009 bytes MEM: Free's : 27 free's of 18749009 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_134] | 1 | True | 15.39 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.569s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9989s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10017s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19206573 bytes MEM: Free's : 26 free's of 19206573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_77] | 1 | True | 13.17 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.516s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8920s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8947s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18703661 bytes MEM: Free's : 27 free's of 18703661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_151] | 1 | True | 11.88 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.349s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4189s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4205s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18704077 bytes MEM: Free's : 27 free's of 18704077 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_323] | 1 | True | 17.78 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.523s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8501s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8528s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18702161 bytes MEM: Free's : 27 free's of 18702161 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_92] | 1 | True | 16.86 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3516s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3529s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681189 bytes MEM: Free's : 26 free's of 18681189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_189] | 1 | True | 12.09 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.333s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4144s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4161s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19949997 bytes MEM: Free's : 26 free's of 19949997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_250] | 1 | True | 17.38 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9004s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9040s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18877497 bytes MEM: Free's : 26 free's of 18877497 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_395] | 1 | True | 19.14 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8550s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8573s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18684037 bytes MEM: Free's : 26 free's of 18684037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_98] | 1 | True | 9.76 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3888s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3904s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681453 bytes MEM: Free's : 26 free's of 18681453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_200] | 1 | True | 10.46 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3436s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3450s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18687417 bytes MEM: Free's : 26 free's of 18687417 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_277] | 1 | True | 17.62 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.486s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9241s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9270s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18706745 bytes MEM: Free's : 27 free's of 18706745 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_386] | 1 | True | 19.44 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.361s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3610s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3625s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20237229 bytes MEM: Free's : 26 free's of 20237229 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_418] | 1 | True | 14.15 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.280s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3848s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3858s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18878829 bytes MEM: Free's : 26 free's of 18878829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_177] | 1 | True | 14.85 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7106s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7126s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18996909 bytes MEM: Free's : 26 free's of 18996909 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_25] | 1 | True | 23.12 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.566s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11177s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11207s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19729485 bytes MEM: Free's : 26 free's of 19729485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_309] | 1 | True | 12.26 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.546s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9888s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9917s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20594489 bytes MEM: Free's : 27 free's of 20594489 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_356] | 1 | True | 13.53 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.485s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5811s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5830s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18704893 bytes MEM: Free's : 27 free's of 18704893 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_32] | 1 | True | 12.87 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.486s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7800s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7827s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 24124661 bytes MEM: Free's : 27 free's of 24124661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_229] | 1 | True | 14.72 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.541s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9074s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9103s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18684461 bytes MEM: Free's : 26 free's of 18684461 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_199] | 1 | True | 23.77 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.528s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9144s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9172s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18701369 bytes MEM: Free's : 27 free's of 18701369 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_396] | 1 | True | 19.83 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.458s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8015s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8039s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18702529 bytes MEM: Free's : 27 free's of 18702529 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_401] | 1 | True | 9.39 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3526s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3540s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18711521 bytes MEM: Free's : 27 free's of 18711521 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_110] | 1 | True | 14.84 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.397s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5459s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5479s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18689133 bytes MEM: Free's : 26 free's of 18689133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_342] | 1 | True | 14.97 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.513s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8918s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8943s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699685 bytes MEM: Free's : 27 free's of 18699685 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_134] | 1 | True | 11.96 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.542s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9714s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9740s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19225389 bytes MEM: Free's : 27 free's of 19225389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_413] | 1 | True | 11.04 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4470s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4573s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18748929 bytes MEM: Free's : 27 free's of 18748929 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_59] | 1 | True | 33.54 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.485s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8118s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8144s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 819792813 bytes MEM: Free's : 26 free's of 819792813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_244] | 1 | True | 16.07 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8542s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8567s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18748985 bytes MEM: Free's : 27 free's of 18748985 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_140] | 1 | True | 11.00 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3388s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3399s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19401645 bytes MEM: Free's : 26 free's of 19401645 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_98] | 1 | True | 21.62 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.264s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3337s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3346s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699733 bytes MEM: Free's : 27 free's of 18699733 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_37] | 1 | True | 11.34 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.261s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3704s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3714s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23509933 bytes MEM: Free's : 26 free's of 23509933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_307] | 1 | True | 12.98 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.516s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9819s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9851s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19307465 bytes MEM: Free's : 27 free's of 19307465 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_297] | 1 | True | 16.51 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.535s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6992s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7008s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18801901 bytes MEM: Free's : 26 free's of 18801901 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_190] | 1 | True | 19.89 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.362s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3792s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3802s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20433837 bytes MEM: Free's : 26 free's of 20433837 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_365] | 1 | True | 9.14 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4956s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4965s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702189 bytes MEM: Free's : 26 free's of 18702189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_405] | 1 | True | 16.44 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.511s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10779s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10809s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18712001 bytes MEM: Free's : 27 free's of 18712001 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_397] | 1 | True | 9.64 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3605s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3618s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18684225 bytes MEM: Free's : 26 free's of 18684225 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_97] | 1 | True | 18.25 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.443s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7079s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7109s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699677 bytes MEM: Free's : 27 free's of 18699677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_289] | 1 | True | 15.97 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.415s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7177s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7200s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18730313 bytes MEM: Free's : 27 free's of 18730313 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_130] | 1 | True | 12.20 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.279s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5814s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5831s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18813357 bytes MEM: Free's : 26 free's of 18813357 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_82] | 1 | True | 22.04 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.600s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11358s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11388s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18722605 bytes MEM: Free's : 27 free's of 18722605 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_109] | 1 | True | 19.04 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3858s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3873s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18707277 bytes MEM: Free's : 27 free's of 18707277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_439] | 1 | True | 21.90 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8214s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8235s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 21873729 bytes MEM: Free's : 27 free's of 21873729 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_361] | 1 | True | 13.07 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8254s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8282s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18720209 bytes MEM: Free's : 27 free's of 18720209 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_227] | 1 | True | 15.56 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.486s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7319s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7333s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18702393 bytes MEM: Free's : 27 free's of 18702393 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_103] | 1 | True | 9.68 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3716s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3732s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18701229 bytes MEM: Free's : 27 free's of 18701229 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_381] | 1 | True | 19.09 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.495s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7680s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7703s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19031309 bytes MEM: Free's : 27 free's of 19031309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_126] | 1 | True | 18.08 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3865s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3878s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18812589 bytes MEM: Free's : 26 free's of 18812589 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_66] | 1 | True | 21.56 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.41s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.453s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8918s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8943s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699309 bytes MEM: Free's : 27 free's of 18699309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_10] | 1 | True | 10.43 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.385s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3692s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3705s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18809261 bytes MEM: Free's : 26 free's of 18809261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_299] | 1 | True | 11.38 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.303s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3913s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3927s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18851273 bytes MEM: Free's : 27 free's of 18851273 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_65] | 0 | - | 0.21 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------------------------------------------------- | Div | /Div | Layer /Div - op type Div, number of input dims(7) is not supported by TIDL, maximum dimension allowed is 6 | --------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_418] | 1 | True | 13.92 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.530s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11739s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11767s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18897489 bytes MEM: Free's : 27 free's of 18897489 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_57] | 1 | True | 14.36 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.438s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5315s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5334s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 64574661 bytes MEM: Free's : 27 free's of 64574661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_331] | 1 | True | 13.17 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.434s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4202s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4218s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18743889 bytes MEM: Free's : 27 free's of 18743889 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_190] | 1 | True | 12.50 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7850s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7876s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20321165 bytes MEM: Free's : 27 free's of 20321165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_334] | 1 | True | 17.78 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.355s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4540s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4555s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18856749 bytes MEM: Free's : 26 free's of 18856749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_393] | 1 | True | 11.86 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 0 | ------------------------------------------------------------------------------ Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.360s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3789s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3802s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671273 bytes MEM: Free's : 26 free's of 18671273 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_267] | 1 | True | 12.05 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.536s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8462s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8490s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700041 bytes MEM: Free's : 27 free's of 18700041 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_250] | 1 | True | 17.94 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7586s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7616s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18895721 bytes MEM: Free's : 27 free's of 18895721 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_392] | 1 | True | 11.25 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6700s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6710s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682021 bytes MEM: Free's : 26 free's of 18682021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_107] | 1 | True | 10.66 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.524s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8018s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8040s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18701349 bytes MEM: Free's : 27 free's of 18701349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_169] | 1 | True | 23.10 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.283s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2750s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2761s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18759981 bytes MEM: Free's : 26 free's of 18759981 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_10] | 1 | True | 12.77 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.308s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3988s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4008s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18827717 bytes MEM: Free's : 27 free's of 18827717 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_246] | 1 | True | 12.76 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.535s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9130s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9160s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730053 bytes MEM: Free's : 26 free's of 18730053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_317] | 1 | True | 12.64 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.561s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9353s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9386s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681585 bytes MEM: Free's : 26 free's of 18681585 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_360] | 1 | True | 14.08 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.3345s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11110s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11135s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701773 bytes MEM: Free's : 26 free's of 18701773 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_116] | 1 | True | 15.45 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4363s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4378s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18709829 bytes MEM: Free's : 27 free's of 18709829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_296] | 1 | True | 12.02 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.510s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7833s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7855s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18799209 bytes MEM: Free's : 26 free's of 18799209 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_17] | 1 | True | 21.79 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3960s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3972s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 51231557 bytes MEM: Free's : 27 free's of 51231557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_340] | 1 | True | 9.06 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3677s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3692s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19622829 bytes MEM: Free's : 26 free's of 19622829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_16] | 1 | True | 16.17 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3420s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3431s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 26838853 bytes MEM: Free's : 27 free's of 26838853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_188] | 1 | True | 16.97 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2975s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2991s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19949997 bytes MEM: Free's : 26 free's of 19949997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_354] | 1 | True | 14.29 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6677s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6710s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18705553 bytes MEM: Free's : 27 free's of 18705553 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_22] | 1 | True | 20.46 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.464s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9027s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9050s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18786221 bytes MEM: Free's : 26 free's of 18786221 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_227] | 1 | True | 20.46 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.283s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3284s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3295s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18684061 bytes MEM: Free's : 26 free's of 18684061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_276] | 1 | True | 16.48 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6545s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6574s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18688377 bytes MEM: Free's : 26 free's of 18688377 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_1] | 1 | True | 20.51 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.517s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8606s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8633s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18704929 bytes MEM: Free's : 27 free's of 18704929 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_357] | 1 | True | 9.20 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.338s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4221s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4238s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18686477 bytes MEM: Free's : 26 free's of 18686477 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_165] | 1 | True | 12.74 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.350s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3943s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3956s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701421 bytes MEM: Free's : 26 free's of 18701421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_109] | 1 | True | 20.70 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 0 | ------------------------------------------------------------------------------ Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.326s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4546s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4577s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18676093 bytes MEM: Free's : 26 free's of 18676093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_272] | 1 | True | 18.31 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3391s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3402s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18701273 bytes MEM: Free's : 27 free's of 18701273 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_329] | 1 | True | 16.41 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7099s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7118s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724417 bytes MEM: Free's : 26 free's of 18724417 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_6] | 1 | True | 17.20 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.492s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8902s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8923s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19452705 bytes MEM: Free's : 27 free's of 19452705 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_340] | 1 | True | 10.70 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3467s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3484s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19641169 bytes MEM: Free's : 27 free's of 19641169 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_158] | 1 | True | 9.60 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6045s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6064s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18687661 bytes MEM: Free's : 26 free's of 18687661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_201] | 1 | True | 22.64 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.557s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9593s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9627s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18687629 bytes MEM: Free's : 26 free's of 18687629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_380] | 1 | True | 11.74 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.269s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3611s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3622s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19031309 bytes MEM: Free's : 27 free's of 19031309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_172] | 1 | True | 9.52 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5511s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5531s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18761517 bytes MEM: Free's : 26 free's of 18761517 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_20] | 1 | True | 20.79 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.578s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10937s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10964s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18795589 bytes MEM: Free's : 27 free's of 18795589 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_434] | 1 | True | 21.23 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7877s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7900s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 21858129 bytes MEM: Free's : 27 free's of 21858129 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_167] | 1 | True | 9.45 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.384s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4310s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4323s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18759733 bytes MEM: Free's : 26 free's of 18759733 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_393] | 1 | True | 13.83 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.486s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9642s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9666s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18702289 bytes MEM: Free's : 27 free's of 18702289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_335] | 1 | True | 18.55 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3960s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3969s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18875729 bytes MEM: Free's : 27 free's of 18875729 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_123] | 1 | True | 18.80 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3933s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3950s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18714285 bytes MEM: Free's : 26 free's of 18714285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_328] | 1 | True | 10.93 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.511s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6833s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6866s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18695469 bytes MEM: Free's : 26 free's of 18695469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_387] | 1 | True | 8.97 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.376s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8245s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8264s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19991637 bytes MEM: Free's : 26 free's of 19991637 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_80] | 1 | True | 11.85 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.349s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4423s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4447s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18698541 bytes MEM: Free's : 26 free's of 18698541 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_187] | 1 | True | 21.36 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.308s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3976s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3991s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19942485 bytes MEM: Free's : 26 free's of 19942485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_431] | 1 | True | 18.20 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.528s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9119s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9149s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19498049 bytes MEM: Free's : 27 free's of 19498049 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_265] | 1 | True | 9.68 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3972s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3986s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19762093 bytes MEM: Free's : 26 free's of 19762093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_348] | 1 | True | 10.84 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4077s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4097s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700725 bytes MEM: Free's : 27 free's of 18700725 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_369] | 1 | True | 18.17 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4852s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4869s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18782289 bytes MEM: Free's : 27 free's of 18782289 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_319] | 1 | True | 20.58 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3199s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3212s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699937 bytes MEM: Free's : 27 free's of 18699937 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_390] | 1 | True | 10.40 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5117s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5127s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20419469 bytes MEM: Free's : 27 free's of 20419469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_416] | 1 | True | 12.55 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.351s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5796s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5811s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18749229 bytes MEM: Free's : 26 free's of 18749229 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_115] | 1 | True | 12.84 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.528s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9445s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9473s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18689325 bytes MEM: Free's : 26 free's of 18689325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_62] | 0 | - | 0.34 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 0 | 0 | | CPU | 1 | x | ------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | --------------------------------------------------------------------------------------------------------------------------------- | Div | /Div | Layer /Div - op type Div, number of input dims(7) is not supported by TIDL, maximum dimension allowed is 6 | --------------------------------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_5] | 1 | True | 17.33 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.537s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10685s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10714s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18715949 bytes MEM: Free's : 26 free's of 18715949 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_371] | 1 | True | 16.20 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.320s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3353s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3366s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18762837 bytes MEM: Free's : 26 free's of 18762837 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_263] | 1 | True | 13.73 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7210s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7229s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19490909 bytes MEM: Free's : 27 free's of 19490909 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_416] | 1 | True | 16.09 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4625s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4640s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18762689 bytes MEM: Free's : 27 free's of 18762689 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_53] | 1 | True | 9.91 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5213s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5232s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22158253 bytes MEM: Free's : 26 free's of 22158253 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_398] | 1 | True | 22.77 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.567s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10717s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10747s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18684581 bytes MEM: Free's : 26 free's of 18684581 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_2] | 1 | True | 22.17 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.492s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8882s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8907s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18702561 bytes MEM: Free's : 27 free's of 18702561 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_104] | 1 | True | 14.60 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.337s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9378s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9388s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18683181 bytes MEM: Free's : 26 free's of 18683181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_170] | 1 | True | 14.80 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3452s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3467s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18765741 bytes MEM: Free's : 26 free's of 18765741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_38] | 1 | True | 21.74 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.206s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6360s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6366s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23156653 bytes MEM: Free's : 26 free's of 23156653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_259] | 1 | True | 18.05 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4405s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4421s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19488569 bytes MEM: Free's : 27 free's of 19488569 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_203] | 1 | True | 20.99 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.388s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6691s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6706s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18707897 bytes MEM: Free's : 27 free's of 18707897 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_101] | 1 | True | 18.31 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6077s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6087s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18701133 bytes MEM: Free's : 27 free's of 18701133 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_423] | 1 | True | 20.50 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.465s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8520s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8541s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18901569 bytes MEM: Free's : 27 free's of 18901569 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_394] | 1 | True | 17.67 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.249s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3575s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3589s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18684037 bytes MEM: Free's : 26 free's of 18684037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_302] | 1 | True | 10.64 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.437s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7089s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7117s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19154989 bytes MEM: Free's : 26 free's of 19154989 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_23] | 1 | True | 17.14 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.223s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2295s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2306s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18795961 bytes MEM: Free's : 27 free's of 18795961 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_221] | 1 | True | 11.81 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4118s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4134s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700137 bytes MEM: Free's : 27 free's of 18700137 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_31] | 1 | True | 11.98 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7074s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7103s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 60642093 bytes MEM: Free's : 27 free's of 60642093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_424] | 1 | True | 21.88 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.571s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10060s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10098s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954669 bytes MEM: Free's : 26 free's of 18954669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_299] | 1 | True | 13.18 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.277s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2827s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2840s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18845101 bytes MEM: Free's : 26 free's of 18845101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_194] | 1 | True | 10.71 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.368s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5219s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5246s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681365 bytes MEM: Free's : 26 free's of 18681365 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_275] | 1 | True | 10.77 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3365s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18683373 bytes MEM: Free's : 26 free's of 18683373 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_9] | 1 | True | 11.59 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.231s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2903s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2920s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18827717 bytes MEM: Free's : 27 free's of 18827717 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_19] | 1 | True | 9.87 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.237s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2686s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2701s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18779309 bytes MEM: Free's : 26 free's of 18779309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_30] | 1 | True | 20.62 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.408s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6859s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6877s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 52282181 bytes MEM: Free's : 27 free's of 52282181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_357] | 1 | True | 18.56 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.517s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8174s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8199s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18704893 bytes MEM: Free's : 27 free's of 18704893 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_27] | 1 | True | 14.37 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.44s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.47s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.634s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9254s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9286s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19817261 bytes MEM: Free's : 27 free's of 19817261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_407] | 1 | True | 10.13 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.392s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5129s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5151s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18694397 bytes MEM: Free's : 26 free's of 18694397 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_397] | 1 | True | 19.75 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6255s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6279s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18702769 bytes MEM: Free's : 27 free's of 18702769 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_132] | 1 | True | 15.88 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.453s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9602s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9630s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18871109 bytes MEM: Free's : 27 free's of 18871109 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_225] | 1 | True | 13.24 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3869s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3880s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681981 bytes MEM: Free's : 26 free's of 18681981 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_54] | 1 | True | 13.84 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.247s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2943s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2954s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 22065985 bytes MEM: Free's : 27 free's of 22065985 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_93] | 1 | True | 11.08 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.352s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3829s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3840s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699629 bytes MEM: Free's : 27 free's of 18699629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_196] | 1 | True | 14.63 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.386s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4061s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4081s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700841 bytes MEM: Free's : 27 free's of 18700841 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_164] | 1 | True | 9.49 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.414s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5196s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5212s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18719885 bytes MEM: Free's : 27 free's of 18719885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_72] | 1 | True | 9.54 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8890s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8919s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700333 bytes MEM: Free's : 27 free's of 18700333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_378] | 1 | True | 20.43 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.326s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5288s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5309s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19108689 bytes MEM: Free's : 27 free's of 19108689 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_215] | 1 | True | 11.39 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7265s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7285s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19264313 bytes MEM: Free's : 27 free's of 19264313 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_239] | 1 | True | 14.75 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.493s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9263s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9289s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18712061 bytes MEM: Free's : 27 free's of 18712061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_228] | 1 | True | 23.80 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10754s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10786s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18684061 bytes MEM: Free's : 26 free's of 18684061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_320] | 1 | True | 9.87 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2712s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2724s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681773 bytes MEM: Free's : 26 free's of 18681773 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_160] | 1 | True | 15.38 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.813s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7789s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7810s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18719021 bytes MEM: Free's : 27 free's of 18719021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_264] | 1 | True | 17.43 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.349s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4012s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4027s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19471789 bytes MEM: Free's : 26 free's of 19471789 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_361] | 1 | True | 17.19 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.545s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8666s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8687s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701773 bytes MEM: Free's : 26 free's of 18701773 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_213] | 1 | True | 13.23 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.463s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5848s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5877s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19100845 bytes MEM: Free's : 26 free's of 19100845 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_215] | 1 | True | 15.44 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8663s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8700s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19245997 bytes MEM: Free's : 26 free's of 19245997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_15] | 1 | True | 14.50 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.557s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9497s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9522s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26819501 bytes MEM: Free's : 26 free's of 26819501 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_372] | 1 | True | 18.28 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.411s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3891s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3905s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18783309 bytes MEM: Free's : 27 free's of 18783309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_327] | 1 | True | 11.26 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.340s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4066s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4079s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18710609 bytes MEM: Free's : 27 free's of 18710609 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_338] | 1 | True | 15.49 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.523s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7717s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7745s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19380909 bytes MEM: Free's : 26 free's of 19380909 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_216] | 1 | True | 21.37 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.320s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3765s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3778s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681213 bytes MEM: Free's : 26 free's of 18681213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_367] | 1 | True | 13.35 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.519s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9144s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9178s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18781089 bytes MEM: Free's : 27 free's of 18781089 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_380] | 1 | True | 14.60 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.536s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9147s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9178s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19012269 bytes MEM: Free's : 26 free's of 19012269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_274] | 1 | True | 9.96 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.269s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6834s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6846s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18701465 bytes MEM: Free's : 27 free's of 18701465 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_412] | 1 | True | 13.46 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1702s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8469s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8489s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18753489 bytes MEM: Free's : 27 free's of 18753489 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_293] | 1 | True | 15.31 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3619s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3635s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18799597 bytes MEM: Free's : 26 free's of 18799597 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_100] | 1 | True | 15.92 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.385s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3817s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3827s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699781 bytes MEM: Free's : 27 free's of 18699781 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_50] | 1 | True | 21.06 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10838s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10871s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18876333 bytes MEM: Free's : 26 free's of 18876333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_399] | 1 | True | 17.26 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.383s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9054s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9075s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18703089 bytes MEM: Free's : 27 free's of 18703089 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_255] | 1 | True | 13.72 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.515s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8400s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8425s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18898397 bytes MEM: Free's : 27 free's of 18898397 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_322] | 1 | True | 20.87 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.453s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5871s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5899s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18683837 bytes MEM: Free's : 26 free's of 18683837 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_29] | 1 | True | 13.52 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4226s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4241s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 28642221 bytes MEM: Free's : 26 free's of 28642221 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_159] | 1 | True | 21.64 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.36s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.565s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6683s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6694s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18700597 bytes MEM: Free's : 26 free's of 18700597 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_422] | 1 | True | 19.35 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.570s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8920s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8947s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18901569 bytes MEM: Free's : 27 free's of 18901569 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_282] | 1 | True | 12.81 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.542s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9380s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9408s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18707465 bytes MEM: Free's : 27 free's of 18707465 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_237] | 1 | True | 12.39 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.535s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6958s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6984s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18714425 bytes MEM: Free's : 27 free's of 18714425 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_252] | 1 | True | 20.62 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.369s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5985s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6000s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18878509 bytes MEM: Free's : 26 free's of 18878509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_184] | 1 | True | 16.64 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.586s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12916s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12950s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19962669 bytes MEM: Free's : 27 free's of 19962669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_398] | 1 | True | 21.64 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.259s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3748s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3761s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18703089 bytes MEM: Free's : 27 free's of 18703089 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_122] | 1 | True | 16.49 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.505s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9422s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9447s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18714285 bytes MEM: Free's : 26 free's of 18714285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_261] | 1 | True | 17.13 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.533s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9619s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9651s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19682105 bytes MEM: Free's : 27 free's of 19682105 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_185] | 1 | True | 18.00 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.528s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8020s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8043s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19943853 bytes MEM: Free's : 26 free's of 19943853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_409] | 1 | True | 9.19 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2998s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3010s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18748449 bytes MEM: Free's : 27 free's of 18748449 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_175] | 1 | True | 14.65 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.565s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9379s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9412s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19014477 bytes MEM: Free's : 27 free's of 19014477 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_320] | 1 | True | 17.40 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6228s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6249s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700017 bytes MEM: Free's : 27 free's of 18700017 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_434] | 1 | True | 10.15 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.459s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5168s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5187s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 21838509 bytes MEM: Free's : 26 free's of 21838509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_125] | 1 | True | 22.71 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 0 | ------------------------------------------------------------------------------ Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3949s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3963s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18798973 bytes MEM: Free's : 26 free's of 18798973 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_259] | 1 | True | 11.21 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7570s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7594s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19469485 bytes MEM: Free's : 26 free's of 19469485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_344] | 1 | True | 11.74 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.486s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10815s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10839s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700545 bytes MEM: Free's : 27 free's of 18700545 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_17] | 1 | True | 13.45 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7114s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7137s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 51211181 bytes MEM: Free's : 26 free's of 51211181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_359] | 1 | True | 14.95 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4137s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4154s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701377 bytes MEM: Free's : 26 free's of 18701377 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_222] | 1 | True | 11.45 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.485s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8233s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8264s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681781 bytes MEM: Free's : 26 free's of 18681781 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_184] | 1 | True | 9.86 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9239s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9271s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19943853 bytes MEM: Free's : 26 free's of 19943853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_203] | 1 | True | 17.48 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.353s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4432s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4448s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18689581 bytes MEM: Free's : 26 free's of 18689581 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_373] | 1 | True | 17.35 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.355s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4933s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4951s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18764589 bytes MEM: Free's : 26 free's of 18764589 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_74] | 1 | True | 15.08 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.430s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4980s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5001s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682285 bytes MEM: Free's : 26 free's of 18682285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_295] | 1 | True | 19.84 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.343s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4561s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4573s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18829625 bytes MEM: Free's : 27 free's of 18829625 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_69] | 1 | True | 10.53 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3690s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3705s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681245 bytes MEM: Free's : 26 free's of 18681245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_402] | 1 | True | 14.54 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.337s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3916s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3931s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18711761 bytes MEM: Free's : 27 free's of 18711761 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_264] | 1 | True | 10.04 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3779s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3794s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19490909 bytes MEM: Free's : 27 free's of 19490909 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_119] | 1 | True | 13.41 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8005s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8030s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18713901 bytes MEM: Free's : 26 free's of 18713901 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_57] | 1 | True | 10.03 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.569s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9896s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9922s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 68750253 bytes MEM: Free's : 26 free's of 68750253 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_36] | 1 | True | 19.49 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.292s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3256s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3264s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23050669 bytes MEM: Free's : 26 free's of 23050669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_389] | 1 | True | 16.59 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.289s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3575s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3586s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19999149 bytes MEM: Free's : 26 free's of 19999149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_197] | 1 | True | 16.96 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4640s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4657s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682653 bytes MEM: Free's : 26 free's of 18682653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_223] | 1 | True | 10.32 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5938s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5959s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700149 bytes MEM: Free's : 27 free's of 18700149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_210] | 1 | True | 11.57 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3777s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3794s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18805049 bytes MEM: Free's : 27 free's of 18805049 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_68] | 1 | True | 18.61 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3977s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3993s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681245 bytes MEM: Free's : 26 free's of 18681245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_156] | 1 | True | 11.40 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.394s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13365s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13403s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18686285 bytes MEM: Free's : 26 free's of 18686285 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_338] | 1 | True | 13.55 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.343s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5376s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5401s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19400529 bytes MEM: Free's : 27 free's of 19400529 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_358] | 1 | True | 11.45 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3372s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3387s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18687853 bytes MEM: Free's : 26 free's of 18687853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_211] | 1 | True | 23.56 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.458s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7467s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7486s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18840377 bytes MEM: Free's : 27 free's of 18840377 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_145] | 1 | True | 13.40 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3543s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3560s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682141 bytes MEM: Free's : 26 free's of 18682141 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_229] | 1 | True | 13.65 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4447s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4461s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18702969 bytes MEM: Free's : 27 free's of 18702969 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_204] | 1 | True | 17.24 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9272s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9305s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18725225 bytes MEM: Free's : 27 free's of 18725225 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_321] | 1 | True | 17.95 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.507s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8432s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8458s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18701921 bytes MEM: Free's : 27 free's of 18701921 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_115] | 1 | True | 21.47 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.408s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5059s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5080s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18707717 bytes MEM: Free's : 27 free's of 18707717 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_343] | 1 | True | 21.59 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.386s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7340s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7353s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700465 bytes MEM: Free's : 27 free's of 18700465 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_280] | 1 | True | 16.76 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2906s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2919s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18688425 bytes MEM: Free's : 26 free's of 18688425 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_305] | 1 | True | 18.20 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5737s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5752s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19159597 bytes MEM: Free's : 26 free's of 19159597 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_383] | 1 | True | 12.53 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.525s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8878s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8907s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20009889 bytes MEM: Free's : 27 free's of 20009889 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_420] | 1 | True | 12.35 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.514s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9960s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9993s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18916689 bytes MEM: Free's : 27 free's of 18916689 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_55] | 1 | True | 17.58 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4094s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4109s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 21566661 bytes MEM: Free's : 27 free's of 21566661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_311] | 1 | True | 14.97 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.507s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8857s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8883s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20788025 bytes MEM: Free's : 27 free's of 20788025 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_74] | 1 | True | 13.43 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.550s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9018s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9048s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700589 bytes MEM: Free's : 27 free's of 18700589 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_78] | 1 | True | 14.81 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7645s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7661s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18704941 bytes MEM: Free's : 27 free's of 18704941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_430] | 1 | True | 12.09 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8859s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8883s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19498049 bytes MEM: Free's : 27 free's of 19498049 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_202] | 1 | True | 14.71 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4438s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4453s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18705977 bytes MEM: Free's : 27 free's of 18705977 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_408] | 1 | True | 12.33 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7279s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7304s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18697901 bytes MEM: Free's : 26 free's of 18697901 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_223] | 1 | True | 10.52 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.451s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4964s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4977s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681805 bytes MEM: Free's : 26 free's of 18681805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_392] | 1 | True | 13.71 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7882s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7901s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700545 bytes MEM: Free's : 27 free's of 18700545 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_326] | 1 | True | 13.72 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4013s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4035s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18710609 bytes MEM: Free's : 27 free's of 18710609 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_286] | 1 | True | 22.97 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.255s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2780s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2788s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18710669 bytes MEM: Free's : 26 free's of 18710669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_239] | 1 | True | 16.75 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.527s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7648s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7674s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693613 bytes MEM: Free's : 26 free's of 18693613 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_11] | 1 | True | 12.32 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3792s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3800s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18820013 bytes MEM: Free's : 26 free's of 18820013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_89] | 1 | True | 17.50 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.356s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4699s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4713s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18960813 bytes MEM: Free's : 26 free's of 18960813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_428] | 1 | True | 12.21 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.358s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4400s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4418s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19569489 bytes MEM: Free's : 27 free's of 19569489 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_180] | 1 | True | 19.76 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7146s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7180s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18999981 bytes MEM: Free's : 26 free's of 18999981 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_401] | 1 | True | 18.82 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 0 | ------------------------------------------------------------------------------ Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4043s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4058s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18680505 bytes MEM: Free's : 26 free's of 18680505 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_363] | 1 | True | 14.50 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.320s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3766s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3783s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18719769 bytes MEM: Free's : 27 free's of 18719769 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_152] | 1 | True | 19.88 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.450s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7408s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7433s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18685901 bytes MEM: Free's : 26 free's of 18685901 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_205] | 1 | True | 9.51 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.354s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4312s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4331s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18725945 bytes MEM: Free's : 27 free's of 18725945 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_233] | 1 | True | 22.71 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.555s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8999s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9028s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18703197 bytes MEM: Free's : 27 free's of 18703197 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_9] | 1 | True | 13.15 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.593s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4047s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4059s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18809261 bytes MEM: Free's : 26 free's of 18809261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_195] | 1 | True | 11.16 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.540s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10294s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10329s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699673 bytes MEM: Free's : 27 free's of 18699673 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_413] | 1 | True | 13.06 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7991s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8030s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18730385 bytes MEM: Free's : 26 free's of 18730385 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_292] | 1 | True | 12.44 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8707s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8759s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18817385 bytes MEM: Free's : 27 free's of 18817385 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_314] | 1 | True | 11.95 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3808s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3823s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20603849 bytes MEM: Free's : 27 free's of 20603849 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_258] | 1 | True | 19.78 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.333s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6481s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6494s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19467321 bytes MEM: Free's : 26 free's of 19467321 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_47] | 1 | True | 23.55 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.412s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12026s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12063s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 138218413 bytes MEM: Free's : 26 free's of 138218413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_34] | 1 | True | 17.47 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.270s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6405s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6419s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22949293 bytes MEM: Free's : 26 free's of 22949293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_221] | 1 | True | 13.54 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.549s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10606s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10636s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681805 bytes MEM: Free's : 26 free's of 18681805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_13] | 1 | True | 10.36 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 0 | ------------------------------------------------------------------------------ Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.345s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3940s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3954s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19175805 bytes MEM: Free's : 26 free's of 19175805 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_287] | 1 | True | 16.86 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.286s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2946s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2954s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18712621 bytes MEM: Free's : 26 free's of 18712621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_45] | 1 | True | 13.51 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.326s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5960s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5978s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 43908005 bytes MEM: Free's : 27 free's of 43908005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_390] | 1 | True | 20.88 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.351s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4467s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4483s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20482989 bytes MEM: Free's : 26 free's of 20482989 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_23] | 1 | True | 19.92 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.541s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9245s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9271s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18777581 bytes MEM: Free's : 26 free's of 18777581 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_128] | 1 | True | 19.47 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.414s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8169s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8195s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18862893 bytes MEM: Free's : 27 free's of 18862893 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_226] | 1 | True | 9.58 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9020s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9050s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18702249 bytes MEM: Free's : 27 free's of 18702249 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_91] | 1 | True | 11.15 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.195s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2417s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2423s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699389 bytes MEM: Free's : 27 free's of 18699389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_52] | 1 | True | 10.39 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.517s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9922s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9957s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22061485 bytes MEM: Free's : 26 free's of 22061485 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_271] | 1 | True | 15.09 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.268s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2701s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2713s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18701129 bytes MEM: Free's : 27 free's of 18701129 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_79] | 1 | True | 15.16 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.519s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7873s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7899s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18698293 bytes MEM: Free's : 26 free's of 18698293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_194] | 1 | True | 11.66 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.520s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8807s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8833s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699625 bytes MEM: Free's : 27 free's of 18699625 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_430] | 1 | True | 11.53 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.568s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10126s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10154s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19478829 bytes MEM: Free's : 26 free's of 19478829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_169] | 1 | True | 14.29 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.514s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8683s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8711s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18778413 bytes MEM: Free's : 27 free's of 18778413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_429] | 1 | True | 16.33 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.368s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4423s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4440s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19469585 bytes MEM: Free's : 26 free's of 19469585 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_51] | 1 | True | 13.46 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8239s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8249s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22068397 bytes MEM: Free's : 26 free's of 22068397 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_114] | 1 | True | 16.83 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3694s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3711s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18689325 bytes MEM: Free's : 26 free's of 18689325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_179] | 1 | True | 19.53 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.38s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.523s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9069s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9101s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18996309 bytes MEM: Free's : 26 free's of 18996309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_197] | 1 | True | 14.46 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.467s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6278s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6299s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700985 bytes MEM: Free's : 27 free's of 18700985 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_176] | 1 | True | 10.77 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.289s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3070s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3084s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19015469 bytes MEM: Free's : 27 free's of 19015469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_433] | 1 | True | 10.75 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.467s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9413s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9443s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 21853089 bytes MEM: Free's : 27 free's of 21853089 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_113] | 1 | True | 18.22 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.292s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4020s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4034s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18689085 bytes MEM: Free's : 26 free's of 18689085 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_178] | 1 | True | 11.87 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.514s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10011s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10041s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19020717 bytes MEM: Free's : 26 free's of 19020717 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_270] | 1 | True | 17.88 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3911s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3922s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18701033 bytes MEM: Free's : 27 free's of 18701033 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_156] | 1 | True | 20.15 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.390s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5557s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5571s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18704653 bytes MEM: Free's : 27 free's of 18704653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_348] | 1 | True | 13.93 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4746s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4770s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682381 bytes MEM: Free's : 26 free's of 18682381 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_88] | 1 | True | 20.19 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.348s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5402s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5418s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18979629 bytes MEM: Free's : 27 free's of 18979629 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_235] | 1 | True | 23.58 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.511s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8229s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8258s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18693389 bytes MEM: Free's : 26 free's of 18693389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_345] | 1 | True | 20.93 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6744s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6773s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700545 bytes MEM: Free's : 27 free's of 18700545 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_130] | 1 | True | 10.76 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.309s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3564s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3579s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18831941 bytes MEM: Free's : 27 free's of 18831941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_341] | 1 | True | 13.87 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.590s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9375s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9401s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699581 bytes MEM: Free's : 27 free's of 18699581 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_316] | 1 | True | 9.67 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.358s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5705s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5727s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681173 bytes MEM: Free's : 26 free's of 18681173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_147] | 1 | True | 22.85 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.588s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8895s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8911s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700525 bytes MEM: Free's : 27 free's of 18700525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_155] | 1 | True | 9.99 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3818s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3837s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18704269 bytes MEM: Free's : 27 free's of 18704269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_214] | 1 | True | 19.14 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4048s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4061s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19119929 bytes MEM: Free's : 27 free's of 19119929 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_249] | 1 | True | 11.50 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3637s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3648s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18748333 bytes MEM: Free's : 26 free's of 18748333 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_279] | 1 | True | 23.92 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8019s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8049s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18707321 bytes MEM: Free's : 27 free's of 18707321 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_406] | 1 | True | 9.95 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.433s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5283s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5303s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18712961 bytes MEM: Free's : 27 free's of 18712961 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_198] | 1 | True | 11.35 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.506s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7279s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7301s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682653 bytes MEM: Free's : 26 free's of 18682653 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_303] | 1 | True | 23.71 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.358s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4866s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4888s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19221305 bytes MEM: Free's : 27 free's of 19221305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_382] | 1 | True | 15.15 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.489s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8644s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8677s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 19129229 bytes MEM: Free's : 27 free's of 19129229 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_131] | 1 | True | 12.19 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.351s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5131s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5148s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18831941 bytes MEM: Free's : 27 free's of 18831941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_388] | 1 | True | 12.37 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.281s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3354s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3371s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19999149 bytes MEM: Free's : 26 free's of 19999149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_308] | 1 | True | 20.15 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7618s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7637s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20573241 bytes MEM: Free's : 26 free's of 20573241 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_193] | 1 | True | 11.56 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.340s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4338s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4357s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699625 bytes MEM: Free's : 27 free's of 18699625 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_174] | 1 | True | 15.39 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.466s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7972s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7991s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18800525 bytes MEM: Free's : 27 free's of 18800525 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_198] | 1 | True | 12.17 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.536s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7196s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7215s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700985 bytes MEM: Free's : 27 free's of 18700985 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_294] | 1 | True | 20.44 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.775s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4963s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4977s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18818105 bytes MEM: Free's : 27 free's of 18818105 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_162] | 1 | True | 13.26 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3761s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3773s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701997 bytes MEM: Free's : 26 free's of 18701997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_366] | 1 | True | 13.32 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.309s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3669s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3685s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18726029 bytes MEM: Free's : 27 free's of 18726029 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_186] | 1 | True | 12.78 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3756s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3780s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20091693 bytes MEM: Free's : 27 free's of 20091693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_432] | 1 | True | 12.79 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9564s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9591s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19776429 bytes MEM: Free's : 26 free's of 19776429 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_205] | 1 | True | 20.34 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.230s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4265s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4271s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18707437 bytes MEM: Free's : 26 free's of 18707437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_363] | 1 | True | 19.06 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.423s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7944s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7960s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701397 bytes MEM: Free's : 26 free's of 18701397 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_88] | 1 | True | 15.30 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.513s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6911s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6940s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18960813 bytes MEM: Free's : 26 free's of 18960813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_154] | 1 | True | 14.80 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.549s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9209s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9235s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18704557 bytes MEM: Free's : 27 free's of 18704557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_342] | 1 | True | 18.26 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.235s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2754s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2762s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681321 bytes MEM: Free's : 26 free's of 18681321 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_144] | 1 | True | 13.74 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3926s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3938s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18682141 bytes MEM: Free's : 26 free's of 18682141 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_400] | 1 | True | 11.43 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.587s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11172s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11208s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18685165 bytes MEM: Free's : 26 free's of 18685165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_304] | 1 | True | 13.34 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3166s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3178s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19154025 bytes MEM: Free's : 26 free's of 19154025 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_70] | 1 | True | 13.74 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.509s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8633s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8658s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681261 bytes MEM: Free's : 26 free's of 18681261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_155] | 1 | True | 15.88 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4969s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4977s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18685909 bytes MEM: Free's : 26 free's of 18685909 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_317] | 1 | True | 11.47 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.489s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7993s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8018s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699857 bytes MEM: Free's : 27 free's of 18699857 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_79] | 1 | True | 13.08 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.265s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3314s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3320s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18716493 bytes MEM: Free's : 27 free's of 18716493 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_219] | 1 | True | 12.98 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.362s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5682s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5693s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700041 bytes MEM: Free's : 27 free's of 18700041 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_99] | 1 | True | 12.90 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5055s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5061s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681453 bytes MEM: Free's : 26 free's of 18681453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_14] | 1 | True | 12.43 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.164s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3281s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3284s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 20737349 bytes MEM: Free's : 27 free's of 20737349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_82] | 1 | True | 11.96 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.195s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2208s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2210s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18704301 bytes MEM: Free's : 26 free's of 18704301 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_138] | 1 | True | 8.60 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.277s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2577s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2585s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19208109 bytes MEM: Free's : 26 free's of 19208109 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_423] | 1 | True | 11.34 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.253s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4529s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4534s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18882669 bytes MEM: Free's : 26 free's of 18882669 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_337] | 1 | True | 9.97 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6627s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6634s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19377217 bytes MEM: Free's : 26 free's of 19377217 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_374] | 1 | True | 10.65 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.163s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1868s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1872s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793389 bytes MEM: Free's : 26 free's of 18793389 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_43] | 1 | True | 9.74 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.150s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2273s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2277s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20262829 bytes MEM: Free's : 26 free's of 20262829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_256] | 1 | True | 7.90 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4859s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4865s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18879661 bytes MEM: Free's : 26 free's of 18879661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_222] | 1 | True | 8.97 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4364s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4368s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18700065 bytes MEM: Free's : 27 free's of 18700065 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_289] | 1 | True | 5.70 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.127s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2209s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2211s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18711821 bytes MEM: Free's : 26 free's of 18711821 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_68] | 1 | True | 4.28 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_BatchNormLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 8 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.73s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1691s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1692s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 27 alloc's of 18699469 bytes MEM: Free's : 27 free's of 18699469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Div_Const_118] | 1 | True | 3.61 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ ========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ------------------------------------------------------------------------------ | Layer | Nodes before optimization | Nodes after optimization | ------------------------------------------------------------------------------ | TIDL_ConstDataLayer | 0 | 1 | | TIDL_EltWiseLayer | 1 | 1 | ------------------------------------------------------------------------------ Total nodes in subgraph: 6 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1474s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1477s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18713901 bytes MEM: Free's : 26 free's of 18713901 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||